LP62S1024BU-70LLI datasheet(11/17 Pages) AMICC

Part #	LP62S1024BU-70LLI

Description	128K X 8 BIT LOW VOLTAGE CMOS SRAM

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Manufacturer	AMICC [AMIC Technology]

Direct Link	http://www.amictechnology.com

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LP62S1024B-I Series

(August, 2004, Version 1.2)

10

AMIC Technology, Corp.

AC Test Conditions

Input Pulse Levels

0.4V to 2.4V

Input Rise and Fall Time

5 ns

Input and Output Timing Reference Levels

1.5V

Output Load

See Figures 1 and 2

30pF

* Including scope and jig.

CL

TTL

5pF

CL

TTL

Figure 1. Output Load

Figure 2. Output Load for tCLZ1,

tCLZ2, tOHZ, tOLZ, tCHZ1,

tCHZ2, tWHZ, and tOW

Data Retention Characteristics (TA = -40°C to 85°C)

Symbol

Parameter

Min.

Max.

Unit

Conditions

VDR1

2.0

3.6

V

CE1

≥ VCC - 0.2V

VDR2

VCC for Data Retention

2.0

3.6

V

CE2

≤ 0.2V,

ICCDR1

Data Retention Current

-

1*

µA

VCC = 2V,

CE1

≥ VCC - 0.2V,

VIN

≥ 0V

ICCDR2

-

1*

µA

VCC = 2V,

CE2

≤ 0.2V,

VIN

≥ 0V

tCDR

Chip Disable to Data Retention Time

0

-

ns

See Retention Waveform

tR

Operation Recovery Time

5

-

ms

*

LP62S1024B-55LLI/70LLI

ICCDR: max.

1

µA at TA = 0°C to + 40°C

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