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LP62S1024BX-55LLI Datasheet(PDF) 10 Page - AMIC Technology

Part # LP62S1024BX-55LLI
Description  128K X 8 BIT LOW VOLTAGE CMOS SRAM
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Manufacturer  AMICC [AMIC Technology]
Direct Link  http://www.amictechnology.com
Logo AMICC - AMIC Technology

LP62S1024BX-55LLI Datasheet(HTML) 10 Page - AMIC Technology

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LP62S1024B-I Series
(August, 2004, Version 1.2)
9
AMIC Technology, Corp.
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
CE1
CE2
DIN
tDH
tDW
(4)
(4)
tCW5
tAW
tWR3
WE
DOUT
tWHZ7
tWP2
tCW5
tAS1
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low CE1, a high CE2 and a low WE .
3. tWR is measured from the earliest of CE1 or WE going high or CE2 going low to the end of the Write cycle.
4. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of CE1 going low or CE2 going high to the end of Write.
6. OE is continuously low. ( OE = VIL)
7. Transition is measured
±500mV from steady state. This parameter is sampled and not 100% tested.


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