Data Sheet
INDT/R165B
INDT/R330B
Date: 2005-02-18 Revision: 1.1
Page 5 of 41
The transmitter’s pixel interface accept pixel data with a pixel clock frequency of 24 – 161 MHz (full pixel mode). In single-
ended mode, PX_CLK+ is the clock input and PX_CLK– has to be tied to GND. All pixel data and pixel clock inputs of the
transmitter can be selected through the VREF-pin to either work with conventional graphic controllers with 3.3 V output
voltage swing or to work with latest controllers with low voltage swing (1.0 – 2.0 V, see Figure 3.3
VREF Reference
Circuitry). The pixel data and pixel clock outputs of the receiver provide a 3.3 V CMOS compliant output.
1.2.2 Pixel Interface Modes
The pixel interface is configurable to accommodate all the various graphic interface standards in the market. The width of
the pixel interface is a function of the selected operating mode.
• In half-pixel mode the bit width of the pixel interface is 12-bit. In half-pixel mode the lower and upper 12 bits of a parallel
video interface (24-bit) are transmitted at consecutive sampling edges. This mode is supported only at the Tx devices.
• In full-pixel mode the bit width of the pixel interface can be set to support an 18- or 24-bit wide parallel video interface.
1 pixel per sampling edge is transmitted.
• In double-pixel mode the bit width of the pixel interface can be set to support a 36- or 48-bit wide parallel video
interface. 2 pixels per sampling edge are transmitted.
1.2.3 Pixel Clock Sampling Modes
The pixel interface can be set to support data sampling at the rising, falling or at both edges of the pixel clock,
depending on the selected mode.
Table 1.4 and Figure 1.3, Figure 1.4, Figure 1.5 summarize the various options for configuring the pixel interface.
Pixel Mode
Clock
Edge
PX_CLK+
PX_CLK
Description
both
↑↓
–
12 bits low part of pixel(n) @ rising edge of PX_CLK+
12 bits high part of pixel(n) @ falling edge of PX_CLK+
both
↑↓
–
12 bits low part of pixel(n) @ falling edge of PX_CLK+
12 bits high part of pixel(n) @ rising edge of PX_CLK+
rising
↑↑
12 bits low part of pixel(n) @ rising edge of PX_CLK+
12 bits high part of pixel(n) @ rising edge of PX_CLK
12-bit
(Half Pixel)
TX Only
rising
↑↑
12 bits low part of pixel(n) @ rising edge of PX_CLK
12 bits high part of pixel(n) @ rising edge of PX_CLK+
rising
↑
–
18 bits of pixel(n) sampled at rising edge of PX_CLK+
falling
↓
–
18 bits of pixel(n) sampled at falling edge of PX_CLK+
18-bit
(Full Pixel)
both
↑↓
–
18 bits of pixel(n) sampled at both edges of PX_CLK+
rising
↑
–
24 bits of pixel(n) sampled at rising edge of PX_CLK+
falling
↓
–
24 bits of pixel(n) sampled at falling edge of PX_CLK+
24-bit
(Full Pixel)
both
↑↓
–
24 bits of pixel(n) sampled at both edges of PX_CLK+
rising
↑
–
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at rising edge of PX_CLK+
36-bit
(Double
Pixel)
falling
↓
–
18 bits of pixel(n) and
18 bits of pixel(n+1) sampled at falling edge of PX_CLK+
rising
↑
–
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at rising edge of PX_CLK+
48-bit
(Double
Pixel)
falling
↓
–
24 bits of pixel(n) and
24 bits of pixel(n+1) sampled at falling edge of PX_CLK+
Table 1.4: Overview – Pixel Interface Configurations
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