HY29F800ATT-12 datasheet(7/40 Pages) HYNIX

Part #	HY29F800ATT-12

Description	8 Megabit (1Mx8/512Kx16), 5 Volt-only, Flash Memory

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Manufacturer	HYNIX [Hynix Semiconductor]

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7 / 40 page

7

Rev. 1.1/Feb 02

HY29F800A

Table 3. HY29F800A Bus Operations Requiring High Voltage 1, 2

Notes:

1. L = V

IL, H = VIH, X = Don’t Care.

See DC Characteristics for voltage levels.

2. Address bits not specified are Don’t Care.

3. See text for additional information.

4. SA = sector address. See Table 1.

5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L).

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by placing the byte or word address on the device’s

address inputs while the data to be written is input

on DQ[7:0] in Byte mode (BYTE# = L) and on

DQ[15:0] in Word mode (BYTE# = H). The host

system must drive the CE# and WE# pins Low

and drive OE# High for a valid write operation to

take place. All addresses are latched on the fall-

ing edge of WE# or CE#, whichever happens later.

All data is latched on the rising edge of WE# or

CE#, whichever happens first.

The ‘Device Commands’ section of this document

provides details on the specific device commands

implemented in the HY29F800A.

Output Disable Operation

When the OE# input is at V

IH, output data from the

device is disabled and the data bus pins are placed

in the high impedance state.

Standby Operation

When the system is not reading from or writing to

the HY29F800A, it can place the device in the

Standby mode. In this mode, current consump-

tion is greatly reduced, and the data bus outputs

are placed in the high impedance state, indepen-

dent of the OE# input. The Standby mode can

invoked using two methods.

The device enters the CE# CMOS Standby mode

if the CE# and RESET# pins are both held at V

CC

± 0.5V. Note that this is a more restricted voltage

range than V

IH. If both CE# and RESET# are held

High, but not within V

CC ± 0.5V, the device will be

in the CE# TTL Standby mode, but the standby

current will be greater.

The device enters the RESET# CMOS Standby

mode when the RESET# pin is held at V

SS ± 0.5V.

If RESET# is held Low but not within V

SS ± 0.5V,

the HY29F800A will be in the RESET# TTL

Standby mode, but the standby current will be

greater. See Hardware Reset Operation section

for additional information on the reset operation.

The device requires standard access time (t

CE) for

read access when the device is in either of the

standby modes, before it is ready to read data. If

the device is deselected during erasure or pro-

gramming, it continues to draw active current until

the operation is completed.

Hardware Reset Operation

The RESET# pin provides a hardware method of

resetting the device to reading array data. When

the RESET# pin is driven Low for the minimum

specified period, the device immediately termi-

nates any operation in progress, tri-states the data

bus pins, and ignores all read/write commands for

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