HY29DS162 datasheet(2/48 Pages) HYNIX

Part #	HY29DS162

Description	16 Megabit (2M x 8/1M x 16) Super-Low Voltage, Dual Bank, Simultaneous Read/Write, Flash Memory

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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HY29DS162/HY29DS163

r1.3/Apr 01

GENERAL DESCRIPTION

The HY29DS162/HY29DS163 (HY29DS16x) is a

16 Mbit, 1.8 volt-only CMOS Flash memory orga-

nized as 2,097,152 (2M) bytes or 1,048,576 (1M)

words. The device is available in 48-pin TSOP

and 48-ball FBGA packages. Word-wide data

(x16) appears on DQ[15:0] and byte-wide (x8) data

appears on DQ[7:0].

The HY29DS16x Flash memory array is organized

into 39 sectors in two banks. Bank 1 contains

eight 8 Kbyte boot/parameter sectors and 3 or 7

larger sectors of 64 Kbytes each, depending on

the version of the device. Bank 2 contains the

rest of the memory array, organized as 28 or 24

sectors of 64 Kbytes:

The device features simultaneous read/write op-

eration which allows the host system to invoke a

program or erase operation in one bank and im-

mediately and simultaneously read data from the

other bank, except if that bank has any sectors

marked for erasure, with zero latency. This re-

leases the system from waiting for the completion

of program or erase operations, thus improving

overall system performance.

The HY29DS16x can be programmed and erased

in-system with a single 2.0 volt ± 10% V

CC supply.

Internally generated and regulated voltages are

provided for program and erase operations, so that

the device does not require a higher voltage V

PP

power supply to perform those functions. The de-

vice can also be programmed in standard EPROM

programmers. Access times as low as 120 ns are

offered for timing compatibility with the zero wait

state requirements of high speed microproces-

sors. To eliminate bus contention, the HY29DS16x

has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

The device is compatible with the JEDEC single-

power-supply Flash command set standard. Com-

mands are written to the command register using

standard microprocessor write timings, from where

they are routed to an internal state-machine that

controls the erase and programming circuits.

Device programming is performed a byte/word at

a time by executing the four-cycle Program Com-

mand write sequence. This initiates an internal

algorithm that automatically times the program

pulse widths and verifies proper cell margin. Faster

programming times can be achieved by placing

the HY29DS16x in the Unlock Bypass mode, which

requires only two write cycles to program data in-

stead of four.

The HY29DS16x’s sector erase architecture al-

lows any number of array sectors, in one or both

banks, to be erased and reprogrammed without

affecting the data contents of other sectors. De-

vice erasure is initiated by executing the Erase

Command sequence. This initiates an internal al-

gorithm that automatically preprograms the sec-

tor before executing the erase operation. As dur-

ing programming cycles, the device automatically

times the erase pulse widths and verifies proper

cell margin. Hardware Sector Group Protection

optionally disables both program and erase op-

erations in any combination of the sector groups,

while Temporary Sector Group Unprotect, which

requires a high voltage on one pin, allows in-sys-

tem erasure and code changes in previously pro-

tected sector groups. Erase Suspend enables the

user to put erase on hold in a bank for any period

of time to read data from or program data to any

sector in that bank that is not selected for era-

sure. True background erase can thus be

achieved. Because the HY29DS16x features si-

multaneous read/write capability, there is no need

to suspend to read from a sector located within a

bank that does not contain sectors marked for era-

sure. The device is fully erased when shipped

from the factory.

Addresses and data needed for the programming

and erase operations are internally latched during

write cycles. The host system can detect comple-

tion of a program or erase operation by observing

the RY/BY# pin or by reading the DQ[7] (Data#

Polling) and DQ[6] (Toggle) status bits. Hardware

data protection measures include a low V

CC de-

tector that automatically inhibits write operations

during power transitions.

After a program or erase cycle has been com-

pleted, or after assertion of the RESET# pin (which

terminates any operation in progress), the device

is ready to read data or to accept another com-

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