 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PI7C21P100B Datasheet(PDF) 6 Page - Pericom Semiconductor Corporation |
|
||||||||||||||||||||||||||||||
PI7C21P100B Datasheet(HTML) 6 Page - Pericom Semiconductor Corporation |
|
|
6 / 79 page  PI7C21P100B 2-PORT PCI-X TO PCI-X BRIDGE Page 6 of 79 November 2005 – Revision 1.02 5.2 ORDERING RULES................................................................................................................. 33 6 CLOCKS............................................................................................................................................ 35 6.1 PRIMARY AND SECONDARY CLOCK INPUTS................................................................. 35 6.2 CLOCK JITTER........................................................................................................................ 35 6.3 MODE AND CLOCK FREQUENCY DETERMINATION .................................................... 36 6.3.1 PRIMARY BUS ..................................................................................................................... 36 6.3.2 SECONDARY BUS ............................................................................................................... 36 6.3.3 CLOCK STABILITY.............................................................................................................. 37 6.3.4 DRIVER IMPEDANCE SELECTION ................................................................................... 37 7 RESET ............................................................................................................................................... 38 7.1 PRIMARY INTERFACE RESET............................................................................................. 38 7.2 SECONDARY INTERFACE RESET....................................................................................... 38 7.3 BUS PARKING & BUS WIDTH DETERMINATION............................................................ 40 7.4 SECONDARY DEVICE MASKING ....................................................................................... 40 7.5 ADDRESS PARITY ERRORS................................................................................................. 40 7.6 OPTIONAL BASE ADDRESS REGISTER............................................................................. 40 7.7 OPTIONAL CONFIGURATION ACCESS FROM THE SECONDARY BUS ...................... 41 7.8 SHORT TERM CACHING....................................................................................................... 41 8 CONFIGURATION REGISTERS .................................................................................................. 42 8.1 CONFIGURATION REGISTER SPACE MAP ....................................................................... 42 8.1.1 SIGNAL TYPE DEFINITION ............................................................................................... 43 8.1.2 VENDOR ID REGISTER – OFFSET 00h............................................................................. 43 8.1.3 DEVICE ID REGISTER – OFFSET 00h .............................................................................. 43 8.1.4 COMMAND REGISTER – OFFSET 04h.............................................................................. 43 8.1.5 PRIMARY STATUS REGISTER – OFFSET 04h .................................................................. 44 8.1.6 REVISION ID REGISTER – OFFSET 08h ........................................................................... 45 8.1.7 CLASS CODE REGISTER – OFFSET 08h........................................................................... 45 8.1.8 CACHE LINE SIZE REGISTER – OFFSET 0Ch ................................................................. 45 8.1.9 PRIMARY LATENCY TIMER – OFFSET 0Ch ..................................................................... 45 8.1.10 HEADER TYPE REGISTER – OFFSET 0Ch................................................................... 45 8.1.11 BIST REGISTER – OFFSET 0Ch .................................................................................... 45 8.1.12 LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h .................................. 46 8.1.13 UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h................................... 46 8.1.14 PRIMARY BUS NUMBER REGISTER – OFFSET 18h ................................................... 46 8.1.15 SECONDARY BUS NUMBER REGISTER – OFFSET 18h ............................................. 46 8.1.16 SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h ......................................... 46 8.1.17 SECONDARY LATENCY TIMER REGISTER – OFFSET 18h ........................................ 46 8.1.18 I/O BASE ADDRESS REGISTER – OFFSET 1Ch........................................................... 47 8.1.19 I/O LIMIT REGISTER – OFFSET 1Ch............................................................................ 47 8.1.20 SECONDARY STATUS REGISTER – OFFSET 1Ch ....................................................... 47 8.1.21 MEMORY BASE REGISTER – OFFSET 20h .................................................................. 48 8.1.22 MEMORY LIMIT REGISTER – OFFSET 20h ................................................................. 48 8.1.23 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h.................................... 48 8.1.24 PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h................................... 48 8.1.25 PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h............................ 48 8.1.26 PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch.......................... 49 8.1.27 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h.................................................... 49 8.1.28 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h .................................................. 49 8.1.29 CAPABILITY POINTER – OFFSET 34h ......................................................................... 49 8.1.30 EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h .................................. 49 8.1.31 INTERRUPT LINE REGISTER – OFFSET 3Ch.............................................................. 49 |
Similar Part No. - PI7C21P100B |
|
Similar Description - PI7C21P100B |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
