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24LCS52IST Datasheet(PDF) 4 Page - Microchip Technology |
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24LCS52IST Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 22 page  24AA024/24LC024/24AA025/24LC025 DS21210G-page 4 2004 Microchip Technology Inc. 2.0 PIN DESCRIPTIONS 2.1 SDA Serial Data SDA is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open-drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 k Ω for 100 kHz, 2 kΩ for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.2 SCL Serial Clock The SCL input is used to synchronize the data transfer from and to the device. 2.3 A0, A1, A2 The levels on the A0, A1 and A2 inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. Up to eight 24AA024/24LC024/24AA025/24LC025 devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VCC or VSS. 2.4 WP (24XX024 Only) WP is the hardware write-protect pin. It must be tied to VCC or VSS. If tied to Vcc, hardware write protection is enabled. If WP is tied to Vss, the hardware write protection is disabled. Note that the WP pin is available only on the 24XX024. This pin is not internally connected on the 24LC025. 2.5 Noise Protection The 24AA024/24LC024/24AA025/24LC025 employs a VCC threshold detector circuit which disables the inter- nal erase/write logic if the VCC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. 3.0 FUNCTIONAL DESCRIPTION The 24AA024/24LC024/24AA025/24LC025 supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24AA024/ 24LC024/24AA025/24LC025 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. |
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