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June 20, 2000

79RC32364™

*Notice: The information in this document is subject to change without notice

This allows the system architect to allocate address space according to

the most efficient use of bus bandwidth. For example, stack data may be

accessed always as write-back, while packet data may be best

accessed as write through, for later DMA out to an I/O port.

The RC32364 cache controller works in conjunction with these

attributes, enabling an application to alias a region of physical memory

through multiple virtual spaces. The cache controller will also ensure

that regardless of which address space is used the current copy of data

will be provided when referenced, and it will further guarantee that the

cache is properly managed with respect to main memory.

Debug Support

Debug Support

Debug Support

Debug Support

To facilitate software debug, the RC32364 adds a pair of watch regis-

ters to CP0. When enabled, these registers will cause the CPU to take

an exception when a “watched” address is appropriately accessed.

In addition, the RC32364 implements an Enhanced JTAG interface,

which requires the inclusion of significant amounts of debug support

logic on-chip, facilitating the development of low-cost in-circuit emulation

equipment.

For low-cost In-Circuit Emulation, the RC32364 provides an

Enhanced JTAG interface. This interface consists of two modes of

operation: Run-Time Mode and Real-Time Mode.

The Run-Time Mode provides a standard JTAG interface for on-chip

debugging, and the Real-Time Mode provides additional status pins—

PCST[2:0]—which are used in conjunction with JTAG pins for Real-Time

Trace information at the processor internal clock or any division of the

pipeline clock.

The RC32364 implements the traditional RC4000 model of interrupt

processing. However, this model has been enhanced to benefit real-

time systems.

To speed interrupt exception decoding, the RC32364 adds a sepa-

rate interrupt vector. Unlike the RC3000 family—which utilizes a single

common exception vector for all exception types (including interrupts)—

the RC32364 allows kernel software to enable a separate interrupt

exception vector.

When enabled, this vector location speeds interrupt processing by

allowing software to avoid decoding interrupts from general purpose

exceptions.

Development Tools

Development Tools

Development Tools

Development Tools

An array of tools facilitate rapid development of RC32364-based

systems, allowing a wide variety of customers to take advantage of the

processor’s high-performance capabilities while maintaining short time-

to-market goals.

The RC32364 incorporates an enhanced JTAG debug interface. This

interface uses a small number of pins, combined with on-chip debug

support logic, to enable the development of low-cost in-circuit emulators

for high-speed IDT processors.

Cache Memory

Cache Memory

Cache Memory

Cache Memory

To keep the RC32364’s high-performance pipeline full and operating

efficiently, the RC32364 incorporates on-chip instruction and data

caches that can each be accessed in a single processor cycle. Each

cache has its own 32-bit data path and can be accessed in the same

pipeline clock cycle.

The RC32364 incorporates a two-way set associative on-chip

Instruction Cache. This virtually indexed, physically tagged cache is

8kB in size and parity protected. Because this cache is virtually indexed,

the virtual-to-physical address translation occurs in parallel with the

cache access. The tag holds a 21-bit physical address, a valid bit, lock

bit, a parity bit, and the FIFO replacement bit.

For fast, single cycle data access, the RC32364 includes a 2kB on-

chip data cache that is two-way set associative with a fixed 16-byte

(four words) line size. The data cache is protected with byte parity and

its tag is protected with a single parity bit. It is virtually indexed and

physically tagged to allow simultaneous address translation and data

cache access.

The RC32364 supports a cache-locking feature to critical sections

of code and data into on-chip caches, to guarantee fast accesses. The

implementation of cache-locking is on a “per-line” basis, enabling the

system designer to maximize the efficiency of the system cache.

Writes to external memory—whether cache miss write-backs or

stores to uncached or write-through addresses—use the on-chip write

buffer. The write buffer holds a maximum of four address and data

pairs. The entire buffer is used for a data cache writeback and allows

the processor to proceed in parallel with a memory update.

System interfaces

System interfaces

System interfaces

System interfaces

The RC32364 supports a 32-bit system interface, allowing the CPU

to interface with a lower cost memory system. The main features of the

system interface include:

x

Multiplexed address and data bus with Address Latch Enable

(ALE) signal to demultiplex the A/D bus.

x

Support of variable port widths, including boot device.

x

Support of multiple pipeline to system clock ratios, with the CPU

core frequency being derived from the input system clock.

x

Incorporation of a DMA arbiter, allowing an external master

control of the external bus.

The 32-bit system address/data (A/D) bus is used to transfer

addresses and data between the RC32364 and the rest of the system.

The ALE signal is provided to demultiplex the address from this bus.

The DATAEN* signal indicates the data phase of the A/D bus and DT/R*

indicates the direction of data flow. BE*[3:0] indicates the valid bytes on

the bus. Additional ADDR[3:2] provides incremental address during

burst transfers.

To indicate system interface bus activity, the RC32364 provides a

cycle-in-progress (CIP*) signal. The RD* and WR* signals indicate the

type of cycle in progress. And to terminate cycle in progress, the