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June 20, 2000

79RC32364™

*Notice: The information in this document is subject to change without notice

Figure 1 System Block Diagram

Pin Description Table

Pin Description Table

Pin Description Table

Pin Description Table

The following is a list of the system interface pins available on the RC32364. Pin names ending with an asterisk (*) are active when low.

Pin

Type

Description

System Interface

AD(31:4)

I/O

Addr(31:4)/Data(31:4)

High-order multiplexed address and data bits. Regardless of system byte ordering, AD(31) is the MSB of the address.

AD(3:0)

I/O

Size(3:0)/Data(3:0)

Valid sizes for the RC32364 are as follows:

Other encodings allow future generations to service other transfer sizes. During the data phase, AD[3:0] represents the Data(3:0).

Addr(3:2)

O

Addr(3:2)

Non-multiplexed address lines. These serve as the word within block address for cache refills (Addr(3:2)). The word within block

address bits count in a sub-block ordering.

ALE

O

Address Latch Enable.

This signal provides set-up and hold times around the address phase of the AD bus.

ADS*

O

Address Strobe

This active-low signal indicates valid address and the start of a new bus transaction. The processor asserts ADS* for the entire

address cycle. This is the inverse of the ALE signal.

Table 3 System Interface Pin Descriptions (Page 1 of 4)

RC32364

Clock

32-bit Data

Bus

RC32134

SDRAM

CPU I/F

DRAM Ctl

Serial

PIO

Timers,

UART,

Interrupt Ctl

DMA

Channels

Memory &

I/O Ctl

Address &

Control

Memory

& I/O

PCI Bridge with Arbiter

32-bit, 33Mhz PCI Bus

Size(3)

Size(2)

Size(1)

Size(0)

Transfer

Width

0

0

0

0

16 bytes

00

0

1

1 byte

00

1

0

2 bytes

00

1

1

3 bytes

01

0

0

4 bytes