2

4817DS–RFID–12/05

ATA5590 [Preliminary]

2.

The Structure of ATA5590

Figure 2-1.

Structure of ATA5590

ATA5590 contains the following top level blocks:

• The analog front end, which extracts

– the supply voltage for the IC from the RF beam

– the modulation dips transmitted by the reader

– the control signals indicating the status of the power supply

• The analog front end also contains structures for ESD protection, a low-power oscillator, and

a modulator stage.

• The digital front end, which extract status signals of the link as well as the extracted symbols

• A memory block which is implemented as an EEPROM containing an on chip HV voltage

generator to program the memory

• A register unit, which contains the transmitted commands and parameters

• A main finite state machine (FSM), which controls the frond end and the access mechanism.

• A random number generator, which is used to generate random values for the Aloha and

tree-walker-based anticollision procedures.

• Three different persistent nodes, which are able to store the status of the anticollision routine

over a certain time without any external power.

Please refer to the Application Note “Antenna Matching”.

ESD,

Impedance

Adaptation,

and

PSK Return

Link

Modulator

Rectifier and

POR Generation

RSSI,

DSBM and ASK-

system clock

extractor

Modulator

control

Power Supply

POR

Digital Front End

- Header Control

- Data/EOF Extraction

- Return Link Modulation

Encoder

RF Front End

Finite State Machines (FSM's)

Memory Unit

and Decoders

(EEPROM)

HV Generation

HV Measurement

Unit

Register

and CRC

Units

Preselect, ID, ID_s

Status1 Register

and Control

UHF Transponder IC

Low-power Oscillator

and Clock Center

Random Number Generator

Counter Array