- 3 -

Rev. 1.1 August 2006

K7R323682C

K7R321882C

K7R320982C

FEATURES

FUNCTIONAL BLOCK DIAGRAM

• 1.8V+0.1V/-0.1V Power Supply.

• DLL circuitry for wide output data valid window and future fre-

quency scaling.

• I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/

-0.1V for 1.8V I/O

.

• Separate independent read and write data ports

with concurrent read and write operation

• HSTL I/O

• Full data coherency, providing most current data.

• Synchronous pipeline read with self timed early write.

• Registered address, control and data input/output.

• DDR (Double Data Rate) Interface on read and write ports.

• Fixed 2-bit burst for both read and write operation.

• Clock-stop supports to reduce current.

• Two input clocks (K and K) for accurate DDR timing at clock

rising edges only.

• Two input clocks for output data (C and C) to minimize

clock-skew and flight-time mismatches.

• Two echo clocks (CQ and CQ) to enhance output data

traceability.

• Single address bus.

• Byte write (x9, x18, x36) function.

• Separate read/write control pin (R and W)

• Simple depth expansion with no data contention.

• Programmable output impedance.

• JTAG 1149.1 compatible test access port.

• 165FBGA(11x15 ball array FBGA) with body size of 15x17mm

& Lead Free

R

ADDRESS

W

C

C

D (Data in)

ADD

REG

DATA

REG

CLK

GEN

CTRL

LOGIC

1Mx36

(2Mx18)

MEMORY

ARRAY

WRITE DRIVER

K

K

36 (or 18)

4(or 2)

* -F(E)C(I)

F(E) [Package type]: E-Pb Free, F-Pb

C(I) [Operating Temperature]: C-Commercial, I-Industrial

Org.

Part

Number

Cycle

Time

Access

Time

Unit

X36

K7R323682C-F(E)C(I)30

3.3

0.45

ns

K7R323682C-F(E)C(I)25

4.0

0.45

ns

K7R323682C-F(E)C(I)20

5.0

0.45

ns

X18

K7R321882C-F(E)C(I)30

3.3

0.45

ns

K7R321882C-F(E)C(I)25

4.0

0.45

ns

K7R321882C-F(E)C(I)20

5.0

0.45

ns

X9

K7R320982C-F(E)C(I)30

3.3

0.45

ns

K7R320982C-F(E)C(I)25

4.0

0.45

ns

K7R320982C-F(E)C(I)20

5.0

0.45

ns

SELECT OUTPUT CONTROL

Notes: 1. Numbers in ( ) are for x18 device, x9 device also the same with appropriate adjustments of depth and width.

72

19

19 (or 20)

36 (or 18)

Q(Data Out)

36 (or 18)

36 (or 18)

72

(Echo Clock out)

CQ, CQ

QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Renesas, IDT, NEC and Samsung technology.

(or 20)

(or 36)

(or 36)