White Microelectronics • Phoenix, AZ • (602) 437-1520
7
1
WF128K16, WF256K16-XCX5
FEATURES
s Access Times of 50, 60, 70, 90, 120 and 150ns
s 40 pin Ceramic DIP (Package 303)
s Organized as 128Kx16 and 256Kx16
s Sector Architecture
• 8 equal size sectors of 16KBytes each per chip
• Any combination of sectors can be concurrently erased.
Also supports full chip erase
s 100,000 Erase/Program Cycles Minimum (0
°C to 70°C)
s Data Retention, 10 Years at 125
°C
s Commercial, Industrial and Military Temperature Ranges
5V FLASH MODULE
PRELIMINARY *
s 5 Volt Programming; 5V
±10% Supply
s Low Power CMOS
s Embedded Erase and Program Algorithms
s TTL Compatible Inputs and CMOS Outputs
s Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s Page Program Operation and Internal Program Control Time
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note: Programming information available upon request.
FIG. 1 PIN CONFIGURATION AND BLOCK DIAGRAM
A0-16
Address Inputs
I/O0-15
Data Input/Output
CS1-2
Chip Selects
OE
Output Enable
WE
Write Enable
VCC
+5.0V Power
GND
Ground
PIN DESCRIPTION
128K x 8
128K x 8
A 0-16
OE
WE
CS 1
CS 2
128K x 8
128K x 8
I/O 8-15
I/O 0-7
(1)
(1)
NOTE:
1. CS1 and CS2 are used to select the lower and upper 128Kx16 of the
device. CS1 and CS2 must not be enabled at the same time.
BLOCK DIAGRAM
FOR WF256K16-XCX5
BLOCK DIAGRAM
FOR WF128K16-XCX5
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CS2*/NC
CS1
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
GND
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
VCC
WE
A16
A15
A14
A13
A12
A11
A10
A9
GND
A8
A7
A6
A5
A4
A3
A2
A1
A0
128K x 8
A 0-16
OE
WE
CS 1
128K x 8
I/O 8-15
I/O 0-7
* CS2 for 256Kx16 and NC for 128Kx16
October 1998
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
