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IDT71P74804 Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71P74804 Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 22 page MARCH 2004 DSC-6111/00 ©2003 Integrated Device Technology, Inc. “QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “ 1 18Mb Pipelined QDR™II SRAM Burst of 4 Advance Information IDT71P74204 IDT71P74104 IDT71P74804 IDT71P74604 Features x 18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36) x Separate, Independent Read and Write Data Ports - Supports concurrent transactions x Dual Echo Clock Output x 4-Word Burst on all SRAM accesses x Multiplexed Address Bus One Read or One Write request per clock cycle x DDR (Double Data Rate) Data Bus - Four word burst data per two clock cycles on each port - Four word transfers per clock cycle x Depth expansion through Control Logic x HSTL (1.5V) inputs that can be scaled to receive signals from 1.4V to 1.9V. x Scalable output drivers - Can drive HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V. - Output Impedance adjustable from 35 ohms to 70 ohms x 1.8V Core Voltage (VDD) x 165-ball, 1.0mm pitch, 15mm x 17mm fBGA Package x JTAG Interface Description The IDT QDRIITM Burst of four SRAMs are high-speed synchronous memories with independent, double-data-rate (DDR), read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput, with four data items passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance. Comparing this with standard SRAM common I/O (CIO), single data rate (SDR) devices, a four to one in- crease in data access is achieved at equivalent clock speeds. Consider- ing that QDRII allows clock speeds in excess of standard SRAM de- vices, the throughput can be increased well beyond four to one in most applications. Using independent ports for read and write data access, simplifies system design by eliminating the need for bi-directional buses. All buses associated with the QDRII are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDRII has scalable output impedance on its data output bus and echo clocks, allowing the user to tune the bus for low noise and high performance. The QDRII has a single SDR address bus with read addresses and write addresses multiplexed. The read and write addresses interleave with each occurring a maximum of every other cycle. In the event that no operation takes place on a cycle, the subsequest cycle may begin with either a read or write. During write operations, the writing of individual bytes may be blocked through the use of byte or nibble write control signals. The QDRII has echo clocks, which provide the user with a clock Functional Block Diagram DATA REG ADD REG CTRL LOGIC CLK GEN (Note1) D (Note2) SA R W (Note3) BWx K K C C SELECT OUTPUT CONTROL WRITE DRIVER (Note2) CQ Q (Note1) 18M MEMORY ARRAY CQ Notes 1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36 2) Represents 19 address signal lines for x8 and x9, 18 address signal lines for x18, and 17 address signal lines for x36. 3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” andthereare 2signal lines. 6111 drw16 |
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