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MAX7470 Datasheet(PDF) 4 Page - Maxim Integrated Products |
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MAX7470 Datasheet(HTML) 4 Page - Maxim Integrated Products |
4 / 17 page HDTV Continuously Variable Anti-Aliasing Filters 4 ________________________________________________________________________________________ TIMING CHARACTERISTICS PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Serial-Clock Frequency fSCL 0 400 kHz Bus Free Time Between STOP (P) and START (S) Condition tBUF 1.3 µs Hold Time (Repeated) START (Sr) Condition tHD;STA After this period, the first clock pulse is generated 0.6 µs SCL Pulse-Width Low tLOW 1.3 µs SCL Pulse-Width High tHIGH 0.6 µs Setup Time for a Repeated START (Sr) Condition tSU;STA 0.6 µs Data Hold Time tHD;DAT (Note 5) 0.0 0.9 µs Data Setup Time tSU;DAT 100 ns Rise Time of Both SDA and SCL Signals, Receiving tr 0 300 ns Fall Time of Both SDA and SCL Signals, Receiving tf 0 300 ns Fall Time of SDA Signal, Transmitting tf (Note 6) 20 + 0.1Cb 250 ns Setup Time for STOP (P) Condition tSU;STO 0.6 µs Capacitive Load for Each Bus Line Cb 400 pF Pulse Width of Spikes that Are Suppressed by the Input Filter tSP (Note 7) 0 50 ns (AVDD = +5V ±5%, DVDD = 2.7V to 3.6V, RLOAD = 150Ω to GND, CIN = 0.1µF, TA = 0°C to +85°C, unless otherwise noted. Typical values are at AVDD = 5V, DVDD = 3.3V, TA = +25°C.) Note 1: The filter passband edge is set to code 255. Note 2: The filter passband edge is set to code 40. Note 3: 1H is the total line period, depending on the video standard. For NTSC, this is 63.5µs; for HDTV, the line period is 29.64µs. Note 4: The clamp level is at the sync tip for signals with sync pulses, and at the blanking level otherwise. Note 5: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the undefined region of SCL’s falling edge. Note 6: Cb = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD. Note 7: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns. |
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