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White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com

WED2DL32512V

First Address

Second Address

Third Address

Fourth Address

External

Internal

Internal

Internal

X...X00

X...X01

X...X10

X...X11

X...X01

X....X00

X...X11

X...X10

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

First Address

Second Address

Third Address

Fourth Address

External

Internal

Internal

Internal

X...X00

X...X01

X...X10

X...X11

X...X01

X....X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

TRUTH TABLE

Function

Address

CE

ZZ

ADSC

WRITE

OE

CLK

DQ

Used

Deselected Cycle, Power-Down

None

H

L

L

X

X

L-H

High-Z

Deselected Cycle, Power-Down

None

L

L

L

X

X

L-H

High-Z

SNOOZE MODE, Power-Down

None

X

H

X

X

X

X

High-Z

WRITE Cycle, Begin Burst

External

L

L

L

L

X

L-H

D

READ Cycle, Begin Burst

External

L

L

L

H

L

L-H

Q

READ Cycle, Begin Burst

External

L

L

L

H

H

L-H

High-Z

READ Cycle, Suspend Burst

Current

X

L

H

H

L

L-H

Q

READ Cycle, Suspend Burst

Current

X

L

H

H

H

L-H

High-Z

READ Cycle, Suspend Burst

Current

H

L

H

H

L

L-H

Q

READ Cycle, Suspend Burst

Current

H

L

H

H

H

L-H

High-Z

WRITE Cycle, Suspend Burst

Current

X

L

H

L

X

L-H

D

WRITE Cycle, Suspend Burst

Current

H

L

H

L

X

L-H

D

NOTES:

2. For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW.

3. BWa enables WRITEs to DQa’s and DQPa. BWb enables WRITEs to DQb’s. BWc enables WRITEs to DQc’s. BWd enables WRITEs to DQd’s.

4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

5. Wait states are inserted by suspending burst.

6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.

7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.