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IDT70T15L20BFI Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT70T15L20BFI Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 18 page  6.42 IDT70T16/5L High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 11 PRELIMINARY AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range 70T16/5L20 Com 'l Only 70T16/5L25 Com 'l & Ind Sym bol Param eter M in. M ax. M in. M ax. Unit BUSY TIMING (M/S = VIH) tBAA BUSY Acc e ss Tim e from Ad dres s M atch __ __ 20 __ __ 20 ns tBDA BUSY Dis able Tim e from Ad dres s No t M atche d __ __ 20 __ __ 20 ns tBAC BUSY Ac ce ss Tim e fro m Chip E nab le LOW __ __ 20 __ __ 20 ns tBDC BUSY Dis ab le Tim e fro m Chip E nab le HIGH __ __ 17 __ __ 17 ns tAPS Arb itratio n Prio rity Se t-up Tim e (2) 5 __ __ 5 __ __ ns tBDD BUSY Disab le to Valid Data(3) __ __ 30 __ __ 30 ns tWH W rite Ho ld A fte r BUSY(5) 15 __ __ 17 __ __ ns BUSY TIMING (M/S = VIL) tWB BUSY Inp ut to Write(4) 0 __ __ 0 __ __ ns tWH W rite Ho ld A fte r BUSY(5) 15 __ __ 17 __ __ ns PORT-TO-PORT DELAY TIM ING tWDD W r ite P uls e to D ata De lay(1) __ __ 45 __ __ 50 ns tDDD W rite Data Va lid to Re ad D ata De lay (1) __ __ 35 __ __ 35 ns 5663 tb l 1 3 Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH) 5663 drw 11 tDW tAPS ADDR"A" tWC DATAOUT "B" MATCH tWP R/ W"A" DATAIN "A" ADDR"B" tDH VALID (1) MATCH BUSY"B" tBDA VALID tBDD tDDD (3) tWDD NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/ S=VIL. 2. CEL = CER = VIL. 3. OE = VIL for the reading port. 4. If M/ S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above. 5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A". NOTES: 1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)". 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A". 5. To ensure that a write cycle is completed on Port "B" after contention on Port "A". 6. 'X' in part numbers indicates power rating (S or L). |
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