IDT72T51333L5BB datasheet(9/55 Pages) IDT

Part #	IDT72T51333L5BB

Description	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits

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Manufacturer	IDT [Integrated Device Technology]

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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES

(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

PIN DESCRIPTIONS (CONTINUED)

Symbol &

Name

I/O TYPE

Description

Pin No.

RCLK

Read Clock

HSTL-LVTTL When enabled by

REN, the rising edge of RCLK reads data from the selected queue via the output

(T10)

INPUT

bus Qout. The queue to be read is selected via the RDADD address bus and a rising edge of RCLK

while RADEN is HIGH. A rising edge of RCLK in conjunction with ESTR and RDADD will also select the

PAEnflagquadranttobeplacedonthePAEnbusduringdirectflagoperation.Duringpolledflagoperation

the

PAEnbusiscycledwithrespecttoRCLKandtheESYNCsignalissynchronizedtoRCLK.ThePAE

and

OV outputs are all synchronized to RCLK. During device expansion the EXO and EXI signals are

based on RCLK. RCLK must be continuous and free-running.

RDADD

Read Address

HSTL-LVTTL For the 8Q device the RDADD bus is 6 bits. The RDADD bus is a dual purpose address bus. The first

[5:0]

Bus

INPUT

function of RDADD is to select a queue to be read from. The least significant 3 bits of the bus, RDADD[2:0]

(RDADD5-P16

are used to address 1 of 8 possible queues within a multi-queue device. The most significant 3 bits,

RDADD4-P15

RDADD[5:3] are used to select 1 of 8 possible multi-queue devices that may be connected in expansion

RDADD3-P14

mode. These 3 MSB’s will address a device with the matching ID code. The address present on the

RDADD2-N14

RDADD bus will be selected on a rising edge of RCLK provided that RADEN is HIGH, (note, that data

RDADD1-M16

can be placed on to the Qout bus, read from the previously selected queue on this RCLK edge). On the

RDADD0-M15)

next rising RCLK edge after a read queue select, a data word from the previous queue will be placed onto

the outputs, Qout, regardless of the

RENinput.TwoRCLKrisingedgesafterreadqueueselect,datawill

be placed on to the Qout outputs from the newly selected queue, regardless of

REN duetothefirstword

fallthrougheffect.

The second function of the RDADD bus is to select the device of queues to be loaded on to the

PAEnbus

during strobed flag mode. The most significant 3 bits, RDADD[5:3] are again used to select 1 of 8

possible multi-queue devices that may be connected in expansion mode. Address bits RDADD[2:0] are

don’t care during quadrant selection. The quadrant address present on the RDADD bus will be selected

on the rising edge of RCLK provided that ESTR is HIGH, (note, that data can be placed on to the Qout

bus, read from the previously selected queue on this RCLK edge). Please refer to Table 2 for details

on RDADD bus.

REN

Read Enable

HSTL-LVTTL The

REN input enables read operations from a selected queue based on a rising edge of RCLK. A

(T11)

INPUT

queue to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless

ofthestateof

REN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecond

RCLK cycle after queue selection regardless of

REN due to the FWFT operation. A read enable is not

required to cycle the

PAEn bus (in polled mode) or to select the device, (in direct mode).

SCLK

Serial Clock

HSTL-LVTTL If serial programming of the multi-queue device has been selected during master reset, the SCLK input

(N3)

INPUT

clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device

ontherisingedgeofSCLKprovidedthat

SENIisenabled,LOW.Whenexpansionofdevicesisperformed

the SCLK of all devices should be connected to the same source.

SENI

Serial Input

HSTL-LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the

(M2)

Enable

INPUT

part (via a rising edge of SCLK), provided the

SENI input of that device is LOW. If multiple devices are

cascaded, the

SENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial

loading of a given device is complete, its

SENO output goes LOW, allowing the next device in the chain

to be programmed (

SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI

input of the master device (or single device), should be controlled by the user.

SENO

SerialOutput

HSTL-LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device

(M1)

Enable

OUTPUT

has been completed.

SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO

will go LOW after programming provided

SENI is LOW, onceSENI istakenHIGHagain,SENOwillalso

go HIGH. When the

SENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.

If multiple devices are cascaded and serial programming of the devices will be used, the

SENO output

should be connected to the

SENI input of the next device in the chain. When serial programming of the

first device is complete,

SENO will go LOW, thereby taking the SENI input of the next device LOW and

so on throughout the chain. When a given device in the chain is fully programmed the

SENO output

essentiallyfollowsthe

SENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.

When this output goes LOW, serial loading of all devices has been completed.

SI

Serial In

HSTL-LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.

(L1)

INPUT

Data present on SI will be loaded on a rising edge of SCLK provided that

SENI is LOW. In expansion

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