IDT72T51333L5BBI datasheet(8/55 Pages) IDT

Part #	IDT72T51333L5BBI

Description	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72T51333/72T51343/72T51353 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES

(8 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN DESCRIPTIONS (CONTINUED)

Symbol &

Name

I/O TYPE

Description

Pin No.

OV

OutputValid

HSTL-LVTTL Thisoutputflagprovidesoutputvalidstatusforthedatawordpresentonthemulti-queueflow-controldevice

(P9)

Flag

OUTPUT

data output port, Qout. This flag is therefore, 2-stage delayed to match the data output path delay. That

is, there is a 2 RCLK cycle delay from the time a given queue is selected for reads, to the time the

OV flag

represents the data in that respective queue. When a selected queue on the read port is read to empty,

the

OV flag will go HIGH, indicating that data on the output bus is not valid. The OV flag also has High-

Impedance capability, required when multiple devices are used and the

OV flags are tied together.

OW(1)

OutputWidth

LVTTL

OW selects the bus width for the data output bus. If OW is LOW during a Master Reset then the bus width

(L16)

INPUT

is x18, if HIGH then it is x9.

PAE

Programmable

HSTL-LVTTL This pin provides the Almost-Empty flag status for the queue that has been selected on the output port

(P10)

Almost-Empty

OUTPUT

for read operations, (selected via RCLK, RDADD and RADEN). This pin is LOW when the selected

Flag

queue is almost-empty. This flag output may be duplicated on one of the

PAEn bus lines. This flag is

synchronized to RCLK.

PAEn

Programmable

HSTL-LVTTL On the 8Q device the

PAEn bus is 8 bits wide. During a Master Reset this bus is setup for Almost Empty

(

PAE7-P11

Almost-Empty

OUTPUT

mode. This output bus provides

PAE status of all 8 queues within a selected device. During queue

PAE6-P12

Flag Bus

read/write operations these outputs provide programmable empty flag status, in either direct or polled

PAE5-R12

mode. The mode of flag operation is determined during master reset via the state of the FM input. This

PAE4-T12

flag bus is capable of High-Impedance state, this is important during expansion of multi-queue devices.

PAE3-P13

During direct operation the

PAEn bus is updated to show the PAE status of queues within a selected

PAE2-R13

device. Selection is made using RCLK, ESTR and RDADD. During Polled operation the

PAEn bus is

PAE1-T13

loaded with the

PAE status of multi-queue flow-control devices sequentially based on the rising edge

PAE0-T14)

of RCLK.

PAF

Programmable

HSTL-LVTTL This pin provides the Almost-Full flag status for the queue that has been selected on the input port for

(R8)

Almost-FullFlag

OUTPUT

write operations, (selected via WCLK, WRADD and WADEN). This pin is LOW when the selected

queue is almost-full. This flag output may be duplicated on one of the

PAFn bus lines. This flag is

synchronized to WCLK.

PAFn

Programmable

HSTL-LVTTL On the 8Q device the

PAFn bus is 8 bits wide. At any one time this output bus provides PAF status

(

PAF7-P7

Almost-FullFlag

OUTPUT

of all 8 queues within a selected device. During queue read/write operations these outputs provide

PAF6-P6

Bus

programmable full flag status, in either direct or polled mode. The mode of flag operation is determined

PAF5-R6

during master reset via the state of the FM input. This flag bus is capable of High-Impedance state,

PAF4-R7

this is important during expansion of multi-queue devices. During direct operation the

PAFn bus is

PAF3-P5

updated to show the

PAF status of a quadrant of queues within a selected device. Selection is made

PAF2-R5

using WCLK, FSTR, WRADD and WADEN. During Polled operation the

PAFn bus is loaded with the

PAF1-T5

PAF status of multi-queue flow-control device sequentially based on the rising edge of WCLK.

PAF0-T4)

PD

Power Down

HSTL

This input is used to provide additional power savings. When the device I/O is setup for HSTL/eHSTL

(K1)

INPUT

mode a HIGH on the PD input disables the data inputs on the write port only, providing significant power

savings. In LVTTL mode this pin has no operation

PRS

PartialReset

HSTL-LVTTL APartialResetcanbeperformedonasinglequeueselectedwithinthemulti-queuedevice.BeforeaPartial

(T8)

INPUT

Reset can be performed on a queue, that queue must be selected on both the write port and read port

2 clock cycles before the reset is performed. A Partial Reset is then performed by taking

PRS LOW for

one WCLK cycle and one RCLK cycle. The Partial Reset will only reset the read and write pointers to

the first memory location, none of the devices configuration will be changed.

Q[17:0]

Data Output Bus HSTL-LVTTL These are the 18 data output pins. Data is read out of the device via these output pins on the rising edge

Qout (See Pin

OUTPUT

of RCLK provided that

REN is LOW, OE is LOW and the queue is selected. Due to bus matching not

table for details)

all outputs may be used, any unused outputs should not be connected.

RADEN

Read Address

HSTL-LVTTL The RADEN input is used in conjunction with RCLK and the RDADD address bus to select a queue to

(R14)

Enable

INPUT

be read from. A queue addressed via the RDADD bus is selected on the rising edge of RCLK provided

that RADEN is HIGH. RADEN should be asserted (HIGH) only during a queue change cycle(s). RADEN

should not be permanently tied HIGH. RADEN cannot be HIGH for the same RCLK cycle as ESTR. Note,

that a read queue selection cannot be made, (RADEN must NOT go active) until programming of the part

has been completed and

SENO has gone LOW.

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