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TMS320P25 Datasheet(PDF) 3 Page - Texas Instruments |
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TMS320P25 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 48 page  TMS320P25 DIGITAL SIGNAL PROCESSOR SPRS028 – OCTOBER 1994 3 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 architecture The TMS320 family utilizes a modified Harvard architecture for speed and flexibility. In a strict Harvard architecture, program and data memory reside in two separate spaces permitting a full overlap of instruction fetch and execution. The TMS320 family’s modification of the Harvard architecture allows transfers between program and data spaces, thereby increasing the flexibility of the device. This modification permits coefficients stored in program memory to be read into the RAM, eliminating the need for a separate coefficient ROM. It also makes available immediate instructions and subroutines based on computed values. Increased throughput on the TMS320P25 devices for many DSP applications is accomplished by means of single-cycle multiply/accumulate instructions with a data move option, up to eight auxiliary registers with a dedicated arithmetic unit, and faster I/O necessary for data-intensive signal processing. The architectural design of the TMS320P25 emphasizes overall speed, communication, and flexibility in processor configuration. Control signals and instructions provide floating-point support, block-memory transfers, communication to slower off-chip devices, and multiprocessing implementations. |
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