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Table 1-1; PD Class Programming Resistance

for the different types of PD class defined in the IEEE

802.3af Standard. The power modules support the PD

classification protocol with a default ‘Class 0’ signature.

‘Class 0’ corresponds to a 4.42-k

Ω programming resis-

tance, which is set by an internal resistor located between

the ‘Class A’ (pin 12) and ‘Class B’ (pin 11) terminals. By

placing an external resistor across the Class A/B pins (in

parallel with the internal 4.42-k

Ω resistor) the power

module can be made to communicate one of the alternate

classifications to the PSE. Consult Table 1-1 for the

external resistance values.

Under-Voltage Lockout

The UVLO prevents the internal DC/DC converter from

seeing an input voltage until the voltage applied to either

the ‘Data Line A/B’ or ‘Spare Line A/B’ pair of Ethernet

connections approaches 42 V. The UVLO threshold

correlates to a voltage between the ‘Detect B’ (pin 6) and

‘Class B’ (pin 11) terminals of approximately 39.3 V. Only

after the voltage applied from the Ethernet is above the

UVLO threshold is the module’s internal bus voltage

allowed to rise. The internal bus powers the DC/DC

converter and can be measured between the ‘Detect B’

(pin 6) and ‘Input Ref’ (pin 4) terminals.

Input Capacitance

In accordance with the IEEE 802.3af Standard, the

PTB48540 power modules provide an input capacitance

of 0.1 µF to the PSE when communicating the required

detection and classification signatures. Once fully pow-

capacitance of the EMI filter and DC/DC converter;

approximately 7 µF. This capacitance is sufficient to

operate the module’s internal DC/DC converter, and

satisfies the 5 µF minimum capacitance required by the

IEEE 802.3af Standard. For improved hold-up capability,

this input capacitance can be increased with an external

capacitor. Connect the anode of the external capacitor

to ‘Detect B’ (pin 6), and the cathode to the ‘Input Ref’

(pin 4). During power up the power interface IC limits

the inrush current for charging the input capacitance.

Additional capacitance increases the power dissipation in

the IC. For this reason the maximum recommended value

of external capacitance is 220 µF (100-V electrolytic).

Startup

Startup of the module in a PoE application consists of a

complex process of handshaking states between the module

and PSE. During the PD detection state the PSE uses a

low voltage (<10 V) to detect the module’s “valid device”

resistance signature. This is followed by the classification

detection state where the PSE applies a voltage of 15 V

to 20 V to detect the module’s PD class. The PSE con-

tinues to raise the input voltage, but the input voltage to

the internal DC/DC converter is held at zero until the

voltage from the PSE approaches 42 V. At an input voltage

of 42 V or higher, the module’s power interface IC allows

the internal bus voltage to rise using a limited amount of

inrush current. Approximately 50 ms after the DC/DC

converter input filter capacitors are fully charged, the

module is able to produce a regulated output voltage.

Converter Over-Current Protection

The internal DC/DC converter has inherent protection

against an output load fault. Whenever its load current

exceeds the over-current protection threshold (see speci-

fication table) the converter momentarily turns its output

off. After a short period (<100 ms), the regulator will

attempt to power up again by executing a soft-start power

up. The converter will continue in a successive cycle of

shutdown, followed by soft-start power up until the load

fault is removed.

When the DC/DC converter is powered from just the

Ethernet source, a load current above its rated output

(but below its over-current threshold) will likely activate

the over-current protection offered by the power interface

IC. This is especially at input voltages lower than 48 V.

Ethernet Over-Current Protection

Protection is also provided for the Ethernet power source

equipment (PSE). In event of a fault across the module’s

internal bus, the onboard power interface IC limits the

maximum current that may be drawn from the PSE to

no less than 405 mA. This prevents the DC/DC con-

verter from drawing excessive input current and also

safeguards against external faults that may occur across

the ‘Detect B’ (pin 6) and ‘Input Ref’ (pin 4) terminals.

Note: These terminals can be used to add capacitance to the

module’s internal bus.

Load faults applied to the DC/DC converter’s output

will most often trigger the power interface IC’s protec-

tion mechanism prior to activating the converter’s own

current limit threshold. In these instances the power

interface IC will completely shut down the module’s inter-

nal bus. This is a latched condition. It is reset by the PoE

source when it attempts another power-up cycle after it

senses loss of the PD’s Maintain Power Signature (10 mA).

PTB48540 Series