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IDT723664L15PF Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT723664L15PF Datasheet(HTML) 4 Page - Integrated Device Technology |
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4 / 37 page  4 COMMERCIALTEMPERATURERANGE IDT723654/723664/723674 CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 PIN DESCRIPTIONS Symbol Name I/O Description A0-A35 Port A Data I/O 36-bit bidirectional data port for side A. AEA Port A Almost- O Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in Empty Flag FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2. AEB Port B Almost- O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in Empty Flag FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1. AFA Port A Almost- O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty Full Flag locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1. AFB Port B Almost- O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty Full Flag locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2. B0-B35 Port A Data I/O 36-bit bidirectional data port for side B. BE/ FWFT Big-Endian/ I This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. First Word In this case, depending on the bus size, the most significant byte or word on Port A is read from Fall Through Port B first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Select Little-Endian operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFTmust be static throughout device operation. BM(1) Bus-MatchSelect I A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of (Port B) SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation. CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEAare all synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEBare synchronized to the LOW-to-HIGH transition of CLKB. CSA Port A Chip Select I CSAmust be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35 outputs are in the high-impedance state when CSAis HIGH. CSB Port B Chip Select I CSBmust be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. The B0-B35 outputs are in the high-impedance state when CSBis HIGH. EFA/ORA Port A Empty/ O This is a dual function pin. In the IDT Standard mode, the EFAfunction is selected. EFA Output Ready Flag indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORAissynchronizedtotheLOW-to-HIGHtransitionofCLKA. EFB/ORB Port B Empty/ O This is a dual function pin. In the IDT Standard mode, the EFBfunction is selected. EFBindicates Output Ready Flag whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on the B0-B35 outputs, available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. FFA/IRA Port A Full/ O This is a dual function pin. In the IDT Standard mode, the FFAfunction is selected. FFAindicates Input Ready Flag whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA. FFB/IRB Port B Full/ O This is a dual function pin. In the IDT Standard mode, the FFBfunction is selected. FFBindicates Input Ready Flag whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB. |
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