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IDT723664L12PF Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT723664L12PF Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 37 page 8 COMMERCIALTEMPERATURERANGE IDT723654/723664/723674 CMOS SyncBiFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723654/723664/723674 with CLKA andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputsweredisconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below. CALCULATING POWER DISSIPATION With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by: PT = VCC x ICC(f) + Σ(CL x VCC2 x fo) N where: N = number of used outputs (36-bit (long word), 18-bit (word) or 9-bit (byte) bus size) CL = outputcapacitanceload fo = switching frequency of an output Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS) 0 10 20 3040 5060 70 0 50 100 150 200 250 300 VCC = 5.0V fS Clock Frequency MHz fdata = 1/2 fS TA = 25oC CL = 0 pF VCC = 4.5V VCC = 5.5V 5608drw03 80 90 |
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