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DP83251V Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83251V
Description  PLAYER Device (FDDI Physical Layer Controller)
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83251V Datasheet(HTML) 6 Page - National Semiconductor (TI)

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30 Functional Description (Continued)
NRZI TO NRZ DECODER
The NRZI to NRZ Decoder converts Non-Return-To-Zero-
Invert-On-Ones data to Non-Return-To-Zero data
This function can be enabled and disabled through bit 7
(RNRZ) of the Mode Register (MR) When the bit is cleared
it converts the incoming bit stream from NRZI to NRZ
When the bit is set the incoming NRZ bit stream is passed
unchanged
SHIFT REGISTER
The Shift Register converts the serial bit stream into sym-
bol-wide data for the 5B4B Decoder
The Shift Register also provides byte-wide data for the
Framing Logic
FRAMING LOGIC
The Framing Logic performs the Framing function by detect-
ing the beginning of a frame or the Halt-Halt or Halt-Quiet
symbol pair
The J-K symbol pair (11000 10001) indicates the beginning
of a frame during normal operation The Halt-Halt (00100
00100) and Halt-Quiet (00100 00000) symbol pairs are de-
tected during Connection Management (CMT)
Framing can be temporarily suspended (ie framing hold) in
order to maintain data integrity The Framing Hold rules are
explained in Section 81
SYMBOL DECODER
The Symbol Decoder is a two level system The first level is
a 5-bit to 4-bit converter and the second level is a 4-bit
symbol pair to the NSC byte-wide code converter
The first level latches the received 5-bit symbols and de-
codes them into 4-bit symbols Symbols are decoded into
two types data and control The 4-bit symbols are sent to
the Line State Detector and the second level of the Symbol
Decoder See Table 3-1 for the 5B4B Symbol Decoding
list
The second level translates two 4-bit symbols from the 5B
4B converter and the line state information from the Line
State Detector into the National byte-wide code More de-
tails on the National byte-wide code can be found in Section
86
LINE STATE DETECTOR
The FDDI Physical Layer (PHY) standard specifies eight
Line States that the Physical Layer can transmit These Line
States are used in the Connection Management process
They are also used to indicate data within a frame during the
normal operation
The Line State Detector detects nine Line States one more
than the required Line States specified in the standard
The Line States are reported through the Current Receive
State Register (CRSR)
Receive Condition Register A
(RCRA) and Receive Condition Register B (RCRB)
Line States Description
Active Line State
The Line State Detector recognizes the incoming data to be
in the Active Line State upon the reception of the Starting
Delimiter (JK symbol pair)
The Line State Detector continues to indicate Active Line
State while receiving data symbols Ending Delimiter (T
symbols) and Frame Status symbols (R and S) after the JK
symbol pair
Idle Line State
The Line State Detector recognizes the incoming data to be
in the Idle Line State upon the reception of 2 Idle symbol
pairs nominally (plus up to 9 bits of 1 in start up cases)
Idle Line State indicates the preamble of a frame or the lack
for frame transmission during normal operation Idle Line
State is also used in the handshake sequence of the PHY
Connection Management process
TABLE 3-1 Symbol Decoding
Symbol
Incoming 5B
Decoded 4B
0
11110
0000
1
01001
0001
2
10100
0010
3
10101
0011
4
01010
0100
5
01011
0101
6
01110
0110
7
01111
0111
8
10010
1000
9
10011
1001
A
10110
1010
B
10111
1011
C
11010
1100
D
11011
1101
E
11100
1110
F
11101
1111
I (Idle)
11111
1010
H (Halt)
00100
0001
JK (Starting
11000
1101
Delimiter)
10001
T (Ending
01101
0101
Delimiter)
R (Reset)
00111
0110
S (Set)
11001
0111
Q (Quiet)
00000
0010
V (Violation)
00001
0010
V
00010
0010
V
00011
0010
V
00101
0010
V
00110
0010
V
01000
0010
V
01100
0010
V
10000
0010
V
0011
I
1011
Notes
V denotes PHY Invalid or an Elasticity Buffer stuff byte
I denotes Idle symbol in ILS or an Elasticity Buffer stuff byte
Super Idle Line State
The Line State Detector recognizes the incoming data to be
in the Super Idle Line State upon the reception of eight con-
secutive Idle symbol pairs nominally (plus 1 symbol pair)
The Super Idle Line State is used to insure synchronization
6


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