HY62V8400A Series

Rev 06 / Apr. 2001

7

Notes:

1. A write occurs during the overlap of a low /WE and a low /CS.

2. tWR is measured from the earlier of /CS or /WE going high to the end of write cycle.

3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the

output must not be applied.

4. If the /CS low transition occur simultaneously with the /WE low transition or after the

/WE transition, outputs remain in a high impedance state.

5. Q(data out) is the same phase with the write data of this write cycle.

6. Q(data out) is the read data of the next address.

7. Transition is measured + 200mV from steady state.

This parameter is sampled and not 100% tested.

8. /CS in high for the standby, low for active

DATA RETENTION ELECTRIC CHARATERISTIC

(Normal)/-25

°C to 85°C (Extended) /-40°C to 85°C (Industrial), unless otherwise specified.

Symbol

Parameter

Test Condition

Min

Typ

Max

Unit

Vcc for Data Retention

/CS > Vcc - 0.2V,

2.0

-

-

V

Vcc = 3.0V, /CS >Vcc - 0.2V,

LL

-

-

20

uA

LL-E

-

-

30

uA

Data Retention Current

LL-I

-

-

30

uA

tCDR

Chip Deselect to Data

Retention Time

0

-

-

ns

tR

Operating Recovery Time

tRC(2)

-

-

ns

Notes:

°C.

2. tRC is read cycle time.

DATA RETENTION TIMING DIAGRAM

/CS

VDR

/CS > VCC-0.2V

tCDR

tR

VSS

VCC

3.0V

2.2V

DATA RETENTION MODE