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AND8001 Datasheet(PDF) 7 Page - ON Semiconductor |
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AND8001 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 8 page AND8001/D http://onsemi.com 7 Maps show: Ja = 1 JB = AC* Jc = AB Ka = 1 Kb = A Kc = A Figure 8 shows the implementation. Figure 8. Synchronous Divide By 12 CLK AQ BQ CQ OUT, DQ Q Q J C Q Q J C Clk Q Q J C K 50% Out Ja = 1 Jb = AC Jc = AB Jd = ACD Ka = 1 Kb = A Kc = A Kd = ACD KK Q Q J C K HA B C D ABC D 00000 11000 20100 31100 40010 51010* 60001 71001 80101 91101 10 0011 11 1011* The truth table shows that the FF ”D” must change state at 5 and 13 Examination of the truth table shows that the FF ”D” must decode a 5 and a 13 in order to make the desire 50% function. The inputs to the ”D” FF are J = ACD* and K = ACD and requires 3 input AND gates. For larger counters the inputs on the AND gates will need to increase to reach the desired configuration; However for the single digit integers such as 3, 5, 7, & 9 to realize 6, 10, 14, & 18 a fan in of three is max. The methods are expandable. A little observation, thinking, and logic typing will allow the designer to minimize the component count and skew on this type of counter. |
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