IDT72T51256L6BBI datasheet(11/62 Pages) IDT

Part #	IDT72T51256L6BBI

Description	2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits

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Manufacturer	IDT [Integrated Device Technology]

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IDT72T51236/72T51246/72T51256 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES

(4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PIN DESCRIPTIONS (CONTINUED)

REN

Read Enable

HSTL-LVTTL The

RENinputenablesreadoperationsfromaselectedqueuebasedonarisingedgeofRCLK.Aqueue

(T11)

INPUT

to be read from can be selected via RCLK, RADEN and the RDADD address bus regardless of the state

of

REN.DatafromanewlyselectedqueuewillbeavailableontheQoutoutputbusonthesecondRCLK

cycle after queue selection regardless of

RENduetotheFWFToperation.Areadenableisnotrequired

to cycle the

PAEn/PRn bus (in polled mode) or to select the device, (in direct mode).

SCLK

Serial Clock

HSTL-LVTTL If serial programming of the multi-queue device has been selected during master reset, the SCLK input

(N3)

INPUT

clocks the serial data through the multi-queue device. Data setup on the SI input is loaded into the device

ontherisingedgeofSCLKprovidedthat

SENIisenabled,LOW.Whenexpansionofdevicesisperformed

the SCLK of all devices should be connected to the same source.

SENI

Serial Input

HSTL-LVTTL During serial programming of a multi-queue device, data loaded onto the SI input will be clocked into the

(M2)

Enable

INPUT

part (via a rising edge of SCLK), provided the

SENI input of that device is LOW. If multiple devices are

cascaded, the

SENIinputshouldbeconnectedtotheSENOoutputofthepreviousdevice.Sowhenserial

loading of a given device is complete, its

SENO output goes LOW, allowing the next device in the chain

to be programmed (

SENOwillfollowSENIofagivendeviceoncethatdeviceisprogrammed).TheSENI

input of the master device (or single device), should be controlled by the user.

SENO

SerialOutput

HSTL-LVTTL This output is used to indicate that serial programming or default programming of the multi-queue device

(M1)

Enable

OUTPUT

has been completed.

SENOfollowsSENIonceprogrammingofadeviceiscomplete.Therefore,SENO

will go LOW after programming provided

SENI is LOW, once SENI istakenHIGHagain,SENOwillalso

go HIGH. When the

SENOoutputgoesLOW,thedeviceisreadytobeginnormalread/writeoperations.

If multiple devices are cascaded and serial programming of the devices will be used, the

SENO output

should be connected to the

SENI input of the next device in the chain. When serial programming of the

first device is complete,

SENO will go LOW, thereby taking the SENI input of the next device LOW and

so on throughout the chain. When a given device in the chain is fully programmed the

SENO output

essentiallyfollowsthe

SENIinput.TheusershouldmonitortheSENOoutputofthefinaldeviceinthechain.

When this output goes LOW, serial loading of all devices has been completed.

SI

Serial In

HSTL-LVTTL Duringserialprogrammingthispinisloadedwiththeserialdatathatwillconfigurethemulti-queuedevices.

(L1)

INPUT

Data present on SI will be loaded on a rising edge of SCLK provided that

SENI is LOW. In expansion

modetheserialdatainputisloadedintothefirstdeviceinachain.Whenthatdeviceisloadedandits

SENO

hasgoneLOW,thedatapresentonSIwillbedirectlyoutputtotheSOoutput.TheSOpinofthefirstdevice

connects to the SI pin of the second and so on. The multi-queue device setup registers are shift registers.

SO

Serial Out

HSTL-LVTTL This output is used in expansion mode and allows serial data to be passed through devices in the chain

(M3)

OUTPUT

to complete programming of all devices. The SI of a device connects to SO of the previous device in the

chain. The SO of the final device in a chain should not be connected.

TCK(2)

JTAG Clock

LVTTL

ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperations

(A8)

INPUT

of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and

outputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneedstobetiedtoGND.

TDI(2)

JTAG Test Data

LVTTL

OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,

(B9)

Input

INPUT

testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegister

and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.

TDO(2)

JTAG Test Data

LVTTL

OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,

(A9)

Output

OUTPUT

test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register,

ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-

DR and SHIFT-IR controller states.

TMS(2)

JTAG Mode

LVTTL

TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the

(B8)

Select

INPUT

device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.

TRST(2)

JTAG Reset

LVTTL

TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically

(C7)

INPUT

resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.

If the TAP controller is not properly reset then the outputs will always be in high-impedance. If the JTAG

function is used but the user does not want to use

TRST, then TRST can be tied with MRS to ensure

proper queue operation. If the JTAG function is not used then this signal needs to be tied to GND. An

internal pull-up resistor forces

TRSTHIGH if left unconnected.

Symbol &

Name

I/O TYPE

Description

Pin No.

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