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IDT72T51256L5BB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72T51256L5BB Datasheet(HTML) 1 Page - Integrated Device Technology |
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1 / 62 page  1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-6116/2 NOVEMBER 2003 2.5V MULTI-QUEUE FLOW-CONTROL DEVICES (4 QUEUES) 36 BIT WIDE CONFIGURATION 589,824 bits, 1,179,648 bits and 2,359,296 bits IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES ADVANCE INFORMATION IDT72T51236 IDT72T51246 IDT72T51256 Q0 Q3 MULTI-QUEUE FLOW-CONTROL DEVICE FSTR WEN PAF FF WRADD 5 WCLK PAFn x9, x18, x36 DATA IN PAE PR PAEn x9, x18, x36 DATA OUT OE OV Din Qout PRn 4 4 6116 drw01 WADEN ESTR EREN RDADD RADEN ERCLK 5 REN RCLK FUNCTIONAL BLOCK DIAGRAM FEATURES: ••••• Choose from among the following memory density options: IDT72T51236 Total Available Memory = 589,824 bits IDT72T51246 Total Available Memory = 1,179,648 bits IDT72T51256 Total Available Memory = 2,359,296 bits ••••• Configurable from 1 to 4 Queues ••••• Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36 ••••• Independent Read and Write access per queue ••••• User programmable via serial port ••••• User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL ••••• Default multi-queue device configurations -IDT72T51236: 4,096 x 36 x 4Q -IDT72T51246: 8,192 x 36 x 4Q -IDT72T51256: 16,384 x 36 x 4Q ••••• 100% Bus Utilization, Read and Write on every clock cycle ••••• 200 MHz High speed operation (5ns cycle time) ••••• 3.6ns access time ••••• Echo Read Enable & Echo Read Clock Outputs ••••• Individual, Active queue flags (OV, FF, PAE, PAF, PR) ••••• 4 bit parallel flag status on both read and write ports ••••• Provides continuous PAE and PAF status of up to 4 Queues ••••• Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width) ••••• User Selectable Bus Matching Options: - x36in to x36out - x18in to x36out - x9in to x36out - x36in to x18out - x36in to x9out ••••• FWFT mode of operation on read port ••••• Packet mode operation ••••• Partial Reset, clears data in single Queue ••••• Expansion of up to 8 multi-queue devices in parallel is available ••••• Power Down Input provides additional power savings in HSTL and eHSTL modes. ••••• JTAG Functionality (Boundary Scan) ••••• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm ••••• HIGH Performance submicron CMOS technology ••••• Industrial temperature range (-40°C to +85°C) is available |
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