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ADM1178-1ARMZ-R7 Datasheet(PDF) 10 Page - Analog Devices |
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ADM1178-1ARMZ-R7 Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page ADM1178 Preliminary Technical Data Rev. PrD | Page 10 of 16 VOLTAGE AND CURRENT READBACK In addition to providing hot swap functionality, the ADM1178 also contains the components to allow voltage and current readback over an I2C bus. The voltage output of the current sense amplifier and the voltage on the VCC pin are fed into a 12-bit ADC via a multiplexer. The device can be instructed to convert voltage and/or current at any time during operation via an I2C command. When all conversions are complete the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. SERIAL BUS INTERFACE Control of the ADM1178 is carried out via the Inter-IC Bus (I2C). This interface is compatible with fastmode I2C (400 kHz max). The ADM1178 is connected to this bus as a slave device, under the control of a master device. IDENTIFYING THE ADM1178 ON THE I2C BUS The ADM1178 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address. The three MSBs of the address are set to 111 and the two MSBs are set to 10, to give an address 111xx10. Bits A2 and A3 are determined by the state of the ADR pin. There are four different configurations available on the ADR pin which correspond to four different I2C addresses for these bits. These are explained in Table 4 below. This scheme allows four ADM1178 devices to operation on a single I2C bus. Table 4. Setting I2C Addresses via the ADR Pin ADR Configuration Address Low state 0xE4 Resistor to GND 0xEC Floating (unconnected) 0xF4 High state 0xFC GENERAL I2C TIMING Figure 6 and Figure 7 show timing diagrams for general read and write operations using the I2C. The I2C specification defines specific conditions for different types of read and write operation, which are discussed later. The general I2C protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA while the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read). The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device. 2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an acknowledge bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal. If the operation is a write operation, the first data byte after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written. Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the ninth clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition. |
Similar Part No. - ADM1178-1ARMZ-R7 |
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Similar Description - ADM1178-1ARMZ-R7 |
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