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AHA4540-EVB Datasheet(PDF) 2 Page - List of Unclassifed Manufacturers

Part # AHA4540-EVB
Description  TPC EVALUATION BOARD
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Manufacturer  ETC1 [List of Unclassifed Manufacturers]
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AHA4540-EVB Datasheet(HTML) 2 Page - List of Unclassifed Manufacturers

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comtech aha corporation
CONNECTORS
Data I/O
SMA connectors are used for Inputs and outputs
for all high speed serial clock and data interfaces.
The payload side SMA connectors may connect
directly to a BERT transmitter and receiver. The
channel side connections would normally be
through the parallel flat cable connectors. The
parallel connections for the three parallel ports other
than the USER_CDATA use 50 pin twisted pair flat
cables with every other conductor grounded.
Control Port
RS232 connection to the host PC is through a 9-
pin DC shell connector located on the back of the
board. Configuration and monitoring of the EVB
operation is done through this port. A pentium class
PC running Windows OS is required.
Power
5.0V Power is supplied by the user’s power
supply. Maximum current required is 2.0 Amps.
FUNCTIONAL OVERVIEW
The AHA4540 simultaneously encodes and
decodes user provided data using Turbo Product
Codes (TPCs). User provided data is clocked into
the EVB serially using signals S-UCLK and
S_UDATA from coaxial SMA connectors, or with
parallel 8-bit transfers using USER_UDATA from
the parallel connector JP3 and ready/accept
handshake signals. In Figure 1, CPLD_1 contains
the multiplexor that selects either serial data with
clock, or parallel data from the USER_UDATA bus.
Control of this multiplexor is via the AHAESB
Windows software provided. The TPC encoder in
the AHA4540 device encodes the data, adds FEC
bits, then outputs the data to CPLD_3 where the
data gets serialized and transmitted to the channel
along with the clock, S_EDATA and S_ECLK, and
also driven out in 8-bit wide format to the
USER_EDATA bus on JP4.
Once the data is output from the evalutation
board on either the serial or parallel encoded data
interfaces, it is transmitted through an external
channel where the data is corrupted by the addition
of noise resulting in data bit errors. This corrupted
data is clocked into the evaluation board serially
using S_CCLK and S_CDATA or using the
USER_CDATA 16-bit wide parallel input bus on
JP5.
The S_CDATA signal is useful for wrapping
around hard decision channel data back into the
AHA4540 TPC decoder. For soft decision data the
16-bit parallel port must be used. The CDATA port
of the AHA4540 accepts up to 16-bits per clock
transfers of received channel data. This data may be
I,Q data or soft metrics. The chip can accept up to
four I,Q pairs or four soft metrics per transfer. In
serial streaming mode the received serial channel
data is deserialized into four soft metrics with the
lower 3 bits of each metric forced to zero in the
FPGA. The TPC decoder in the AHA4540 corrects
the data errors and outputs the corrected blocks
through CPLD_2 in both serialized clock and data
format, S_DDATA, S_DCLK, and parallel format
to the USER_DDATA bus on JP2.


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