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Device Address

0

Slave Address

0

1

1 A2 A1 A0 R/W

Fixed

Programmable

Control Register and Command Byte

0

0

0

0

B1

B0

0

0

PCA6107

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

SCPS139B – JANUARY 2006 – REVISED OCTOBER 2006

The address of the PCA6107 is shown in Figure 4.

Figure 4. PCA6107 Address

Address Reference

INPUTS

A2

A1

A0

L

L

L

24 (decimal), 18 (hexadecimal)

L

L

H

25 (decimal), 19 (hexadecimal)

L

H

L

26 (decimal), 1A (hexadecimal)

L

H

H

27 (decimal), 1B (hexadecimal)

H

L

L

28 (decimal), 1C (hexadecimal)

H

L

H

29 (decimal), 1D (hexadecimal)

H

H

L

30 (decimal), 1E (hexadecimal)

H

H

H

31 (decimal), 1F (hexadecimal)

The last bit of the slave address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

Following the successful acknowledgment of the address byte, the bus master sends a command byte that is

stored in the control register in the PCA6107. Two bits of this data byte state the operation (read or write) and

the internal registers (input, output, polarity inversion or configuration) that will be affected. This register can be

Once a new command byte has been sent, the register that was addressed continues to be accessed by reads

until a new command byte has been sent.

Figure 5. Control Register Bits

Command Byte

CONTROL REGISTER BITS

COMMAND BYTE

POWER-UP

REGISTER

PROTOCOL

(HEX)

DEFAULT

B1

B0

0

0

0x00

Input Port

Read byte

xxxx xxxx

0

1

0x01

Output Port

Read/write byte

0000 0000

1

0

0x02

Polarity Inversion

Read/write byte

1111 0000

1

1

0x03

Configuration

Read/write byte

1111 1111

7

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