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OXMPCI954 Datasheet(PDF) 7 Page - Oxford Semiconductor |
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OXMPCI954 Datasheet(HTML) 7 Page - Oxford Semiconductor |
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7 / 121 page  DS-0019 Jun 05 External—Free Release Page 7 OXmPCI954 OXFORD SEMICONDUCTOR LTD. Improvements of the OXmPCI954 over discrete solutions Higher degree of integration: The OXmPCI954 device offers four internal 16C950 high- performance UARTs and an 8-bit Local Bus or a Bi-directional parallel port. Multi-function device: The OXmPCI954 is a multi-function device to enable users to load individual device drivers for the internal serial ports, drivers for the peripheral devices connected to the Local Bus or drivers for the internal parallel port. Quad Internal OX16C950 UARTs The OXmPCI954 device contains four ultra-high performance UARTs, which can increase driver efficiency by using features such as the 128-byte deep transmitter & receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates are up to 60Mbps. Improved access timing: Access to the internal UARTs, require zero or one PCI wait states. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latency: The OXmPCI954 device offers shadowed FIFO levels and Interrupt status registers of the internal UARTs, and the MIO pins. This reduces the device driver interrupt latency. Power management: The OXmPCI954 device complies with the PCI Power Management Specification 1.1 and the Microsoft Communications Device-class Power Management Specification 2.0 (2000). Both functions offer the extended capabilities for Power Management. This achieves significant power savings by enabling device drivers to power down the PCI functions. For function 0, this is through switching off the channel clock, in power state D3. Wake-up (PME# generation) can be requested by either functions. For function 0, this is via the RI# inputs of the UARTs in the power-state D3 or any modem line and SIN inputs of the UARTs in power-state D2. For function 1, this is via the MIO[2] input. Optional EEPROM: The OXmPCI954 device can be reconfigured from an external EEPROM, to the end-user’s requirements. However, this is not normally required in many applications as the default values are sufficient for typical applications. An overrun detection mechanism built into the eeprom controller prevents the PCI system from ‘hanging’ due to an incorrectly programmed eeprom. Subsystem ID and Subsystem Vendor ID In some cases the Subsystem ID and Subsystem Vendor ID can be set via input pins. |
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