DESCRIPTION

s Accepts up to 10.7Gbps data

s < 45ps edge rate

s Gain

s CML/PECL differential inputs

s CML outputs

s Internal 50

s Internal 50

s Available in die or 16-pin (3mm

××××× 3mm) MLF package

FEATURES

3.3V 10Gbps DIFFERENTIAL

CML LINE DRIVER/RECEIVER

WITH INTERNAL TERMINATION

SY58016L

FINAL

APPLICATIONS

s Backplane buffering

s OC-3/OC-192 SONET clock or data distribution/driver

s All GigE clock or data distribution/driver

s Fibre Channel distribution/driver

1

Rev.: A

Amendment: /0

Issue Date:

September 2002

The SY58016L is a high-speed, current mode logic (CML)

differential receiver. It is ideal for interfacing with high

frequency sources. It can be used as Line Receiver, Line

Driver and Limiting Amplifier. The device can be operated

from DC to 10Gbps. The input incorporates internal

temination resistors, and directly interfaces to a CML logic

signal. The output is CML compatible, and includes 50

Ω

load resistors.

FUNCTIONAL BLOCK DIAGRAM

TYPICAL PERFORMANCE

MLF and

16

15

14

13

56

7

8

1

2

3

4

12

11

10

9

Q

/Q

D

/D

50

Ω

50

Ω

50

Ω

50

Ω

400mV Output Swing

100mV Input Swing

50

Ω

50

Ω

Backplane

100mV In

400mV Out

(< 45ps Edge Rate)

SY58016L