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TPS54550PWPR Datasheet(PDF) 10 Page - Texas Instruments |
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TPS54550PWPR Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 27 page  www.ti.com Internal Oscillator VO(PH) VO(SYNC) Power Good (PWRGD) Bootstrap Voltage (BOOT) Error Amplifier Voltage Reference T delay 1000 ƒ s(kHz) ms (5) Bias Voltage (VBIAS) TPS54550 SLVS623A – MARCH 2006 – REVISED APRIL 2006 Figure 4. SYNC Output Waveform Up to 1 mA of current can be drawn for use in an external application circuit. The VBIAS pin must have a bypass capacitor value of 1.0 µF. X7R or X5R The VSENSE pin is compared to an internal grade dielectric ceramic capacitors are recommended reference signal, if the VSENSE is greater than 97% because of their stable characteristics over and no other faults are present, the PWRGD pin temperature. presents a high impedance. A low on the PWRGD pin indicates a fault. The PWRGD pin has been designed to provide a weak pull-down and indicates a fault even when the device is unpowered. If the TPS54550 The BOOT capacitor obtains its charge cycle by cycle has power and has any fault flag set, the TPS54550 from the VBIAS capacitor. A capacitor and small indicates the power is not good by driving the value resistor from the BOOT pin to the PH pins is PWRGD pin low. The following events, singly or in required for operation. The bootstrap connection for combination, indicate power is not good: the high side driver must have a bypass capacitor of 0.1 µF and resistor 24 Ohm. • VSENSE pin out of bounds • Overcurrent • Thermal shutdown The VSENSE pin is the error amplifier inverting input. • UVLO undervoltage The error amplifier is a true voltage amplifier with 1.5 • Input voltage not present (weak pull-down) mA of drive capability with a minimum of 60 dB of • Slow-starting open loop voltage gain and a unity gain bandwidth of • VBIAS voltage is low 2 MHz. Once the PWRGD pin presents a high impedance (i.e., power is good), a VSENSE pin out of bounds condition forces PWRGD pin low (i.e., power is bad) The voltage reference system produces a precision after a time delay. This time delay is a function of the reference signal by scaling the output of a switching frequency and is calculated using temperature stable bandgap circuit. During production Equation 5: testing, the bandgap and scaling circuits are trimmed to produce 0.891 V at the output of the error amplifier, with the amplifier connected as a voltage follower. The trim procedure improves the regulation, since it cancels offset errors in the scaling and error amplifier circuits. The VBIAS regulator provides a stable supply for the internal analog circuits and the low side gate driver. 10 Submit Documentation Feedback |
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