PRELIMINARY
CY7C1462AV25
CY7C1464AV25
CY7C1460AV25
Document #: 38-05354 Rev. *A
Page 8 of 27
Write Cycle Description table for details) inputs is latched into
the device and the write is complete.
The data written during the Write operation is controlled by BW
(BWa,b,c,d,e,f,g,h
for
CY7C1464AV25,
BWa,b,c,d
for
CY7C1460AV25 and BWa,b for CY7C1462AV25) signals. The
CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 provides
byte write capability that is described in the Write Cycle
Description table. Asserting the Write Enable input (WE) with
the selected Byte Write Select (BW) input will selectively write
to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous
self-timed write mechanism has been provided to simplify the
write operations. Byte write capability has been included in
order to greatly simplify Read/Modify/Write sequences, which
can be reduced to simple byte write operations.
Because the CY7C1460AV25/CY7C1462AV25/ CY7C1464AV25
are common I/O devices, data should not be driven into the
device while the outputs are active. The Output Enable (OE)
can be deasserted HIGH before presenting data to the DQ and
DQP (DQa,b,c,d,e,f,g,h/DQPa,b,c,d,e,f,g,h for CY7C1464AV25,
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV25 and DQa,b/DQPa,b
for CY7C1462AV25) inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ and DQP
(DQa,b,c,d,e,f,g,h/
DQPa,b,c,d,e,f,g,h
for
CY7C1464AV25,
DQa,b,c,d/DQPa,b,c,d for CY7C1460AV25 and DQa,b/DQPa,b
for CY7C1462AV25) are automatically three-stated during the
data portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1460AV25/CY7C1462AV25/CY7C1464AV25 has
an on-chip burst counter that allows the user the ability to
supply a single address and conduct up to four WRITE opera-
tions without reasserting the address inputs. ADV/LD must be
driven LOW in order to load the initial address, as described
in the Single Write Access section above. When ADV/LD is
driven HIGH on the subsequent clock rise, the chip enables
(CE1, CE2, and CE3) and WE inputs are ignored and the burst
counter is incremented. The correct BW (BWa,b,c,d,e,f,g,h for
CY7C1460AV25, BWa,b,c,d for CY7C1460AV25 and BWa,b for
CY7C1462AV25) inputs must be driven in each cycle of the
burst write in order to write the correct bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, and CE3, must remain inactive
for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
Second
Address
Third
Address
Fourth
Address
A1,A0
A1,A0
A1,A0
A1,A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min.
Max
Unit
IDDZZ
Sleep mode standby current
ZZ
> V
DD − 0.2V
100
mA
tZZS
Device operation to ZZ
ZZ
> V
DD − 0.2V
2tCYC
ns
tZZREC
ZZ recovery time
ZZ
< 0.2V
2tCYC
ns
tZZI
ZZ active to sleep current
This parameter is sampled
2tCYC
ns
tRZZI
ZZ Inactive to exit sleep current
This parameter is sampled
0
ns
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