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TL16C752BTPTREP Datasheet(PDF) 3 Page - Texas Instruments |
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TL16C752BTPTREP Datasheet(HTML) 3 Page - Texas Instruments |
3 / 35 page TL16C752B-EP 3.3-V DUAL UART WITH 64-BYTE FIFO SGLS153 – FEBRUARY 2003 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION NAME NO. I/O DESCRIPTION D0–D4 D5–D7 44–48, 1–3 I/O Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream. DSRA, DSRB 39, 20 I Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR) DTRA, DTRB 34, 35 O Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A logic low on these pins indicates that the TL16C752B-EP is powered on and ready. These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset. GND 17 Pw r Signal and power ground INTA, INTB 30, 29 O Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space or when a modem status flag is detected. INTA–B are in the high-impedance state after reset. IOR 19 I Read input (active low strobe). A high-to-low transition on IOR loads the contents of an internal register defined by address bits A0–A2 onto the TL16C752B-EP data bus (D0–D7) for access by an external CPU. IOW 15 I Write input (active low strobe). A low to high transition on IOW transfers the contents of the data bus (D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2 and CSA and CSB OPA, OPB 32, 9 0 User defined outputs. This function is associated with individual channels A and B. The state of these pins is defined by the user through the software settings of the MCR register, bit 3. INTA–B are set to active mode and OP to a logic 0 when the MCR–3 is set to a logic 1. INTA–B are set to the 3-state mode and OP to a logic 1 when MCR-3 is set to a logic 0. See bit 3, modem control register (MCR bit 3). The output of these two pins is high after reset. RESET 36 I Reset. RESET resets the internal registers and all the outputs. The UART transmitter output and the receiver input is disabled during reset time. See TL16C752B-EP external reset conditions for initialization details. RESET is an active-high input. RIA, RIB 41, 21 I Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem has received a ringing signal from the telephone line. A low to high transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR) RTSA, RTSB 33, 22 O Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset, these pins are set to high. These pins only affect the transmit and receive operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control operation. RXA, RXB 5, 4 I Receive data input. These inputs are associated with individual serial channel data to the TL16C752B-EP. During the local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX input internally. RXRDYA, RXRDYB 31, 18 O Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a timeout interrupt occurs. They go high when the RX FIFO is empty or there is an error in RX FIFO. TXA, TXB 7, 8 O Transmit data. These outputs are associated with individual serial transmit channel data from the TL16C752B-EP. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input. TXRDYA, TXRDYB 43, 6 O Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of spaces available. They go high when the TX buffer is full. VCC 42 I Power supply inputs. XTAL1 13 I Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figure 10). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates. XTAL2 14 O Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output or buffered a clock output. |
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