250

PS8316

03/15/99

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PI6C105

Precision Clock Synthesizer for Mobile PCs

output and test mode enable.

The PI6C105 is a slave receiver device. It can not be read back.

Sub addressing is not supported. To change one of the control

bytes, all preceding bytes must be sent.

Every byte put on the SDATA line must be 8-bits long (MSB first),

followed by an acknowledge bit generated by the receiving device.

During normal data transfers, SDATA changes only when SCLK is

LOW. Exceptions: A HIGH-to-LOW transition on SDATA while

SCLK is HIGH indicates a “start” condition. A LOW-to-HIGH

transition on SDATA, while SCLK is HIGH, is a “stop” condition

and indicates the end of a data transfer cycle.

7

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Clock Enable Configuration

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Each data transfer is initiated with a start condition and ended

with a stop condition. The first byte after a start condition is always

a 7-bit address byte followed by a read/write bit. (HIGH = read

from addressed device, LOW= write to addressed device). If the

device’s own address is detected, PI6C105 generates an acknowl-

edge by pulling SDATA line LOW during ninth clock pulse, then

accepts the following data bytes until another start or stop condi-

tion is detected.

Following acknowledgment of the address byte (D2), two more

bytes must be sent:

1. “Command Code” byte, and

2. “Byte Count” byte.

Although the data bits on these two bytes are “don’t care,” they

must be sent and acknowledged.