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01/14/04

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7

CM1210

Application Information

Design Considerations

In order to realize the maximum protection against

ESD pulses, care must be taken in the PCB layout to

minimize parasitic series inductances on the Supply/

Ground rails as well as the signal trace segment

between the signal input (typically a connector) and the

ESD protection device. Refer to Figure 3, which illus-

trates an example of a positive ESD pulse striking an

input channel. The parasitic series inductance back to

the positive supply voltage.

An ESD current pulse can rise from zero to its peak

value in a very short time. As an example, a level 4

contact discharge per the IEC61000-4-2 standard

results in a current pulse that rises from zero to 30

Similarly for negative ESD pulses, parasitic series

to drastically increased negative voltage on the line

being protected.

Another consideration is the output impedance of the

power supply for fast transient currents. Most power

supplies exhibit a much higher output impedance to

supply DC output voltage and effective output imped-

ance of the power supply respectively. As an example,

If the inductances and resistance described above are

close to zero, the rail-clamp ESD protection diodes will

do a good job of protection. However, since this is not

possible in practical situations, a bypass capacitor

must be used to absorb the very high frequency ESD

energy. So for any brand of rail-clamp ESD protection

diodes, a bypass capacitor should be connected

cuit diagram below. A value of 0.22µF is adequate.

Ceramic chip capacitors mounted with short printed

circuit board traces are good choices for this applica-

tion. Electrolytic capacitors should be avoided as they

have poor high frequency characteristics. For extra

protection, connect a zener diode in parallel with the

bypass capacitor to mitigate the effects of the parasitic

series inductance inherent in the capacitor. The break-

down voltage of the zener diode should be slightly

higher than the maximum supply voltage.

As a general rule, the ESD Protection Array should be

located as close as possible to the point of entry of

expected electrostatic discharges. The power supply

bypass capacitor mentioned above should be as close

minimum PCB trace lengths to the power supply,

ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also California Micro Devices Application Notes

AP209, “Design Considerations for ESD Protection”

and APxxx, "ESD Protection for USB 2.0 Systems".

Figure 3. Application of Positive ESD Pulse between Input Channel and Ground

N

V

PATH OF ESD CURRENT PULSE I

ONE

CHANNEL

OF

CM1210

CHANNEL

INPUT

GROUND RAIL

POSITIVE SUPPLY RAIL

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

LINE BEING

PROTECTED

ESD

D

0.22µF

1

2

D

0A

20A