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CY7C4255
CY7C4265
Document #: 38-06004 Rev. *B
Page 8 of 22
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
19. When tSKEW2 > minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK +
tSKEW2. The Latency Timing applies only at the Empty Boundary (EF = LOW).
20. The first word is available the cycle after EF goes HIGH, always.
Switching Waveforms (continued)
Reset Timing
tRS
tRSR
Q0– Q17
RS
tRSF
tRSF
tRSF
OE=1
OE=0
REN,WEN,
LD
EF,PAE
FF,PAF,
HF
4255–8
[17]
[18]
D0 (FIRSTVALIDWRITE)
First Data Word Latency after Reset with Simultaneous Read and Write
tSKEW2
WEN
WCLK
Q0 –Q17
EF
REN
OE
tOE
tENS
tOLZ
tDS
RCLK
tREF
tA
tFRL
D1
D2
D3
D4
D0
D1
D0 –D17
4255–9
tA
[19]
[19]
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