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IDT2308A-1H Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT2308A-1H Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 10 page 3 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT2308A 3.3V ZERO DELAY CLOCK MULTIPLIER Device FeedbackFrom Bank A Frequency Bank B Frequency IDT2308A-1 Bank A or Bank B Reference Reference IDT2308A-1H Bank A or Bank B Reference Reference IDT2308A-2 Bank A Reference Reference/2 IDT2308A-2 Bank B 2 x Reference Reference IDT2308A-2H Bank A Reference Reference/2 IDT2308A-2H Bank B 2 x Reference Reference IDT2308A-3 Bank A 2 x Reference Reference or Reference(1) IDT2308A-3 Bank B 4 x Reference 2 x Reference IDT2308A-4 Bank A or Bank B 2 x Reference 2 x Reference NOTE: 1. Output phase is indeterminant (0° or 180° from input clock). AVAILABLE OPTIONS FOR IDT2308A S2 S1 CLK A CLK B Output Source PLL Shut Down L L Tri-State Tri-State PLL Y L H Driven Tri-State PLL N H L Driven Driven REF Y H H Driven Driven PLL N FUNCTION TABLE(1) SELECT INPUT DECODING NOTE: 1. H = HIGH Voltage Level L = LOW Voltage Level ZERO DELAY AND SKEW CONTROL To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are loaded equally, for zero output-output skew. |
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