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Rev. 0 | Page 9 of 52

AC ’97 TIMING PARAMETERS

Guaranteed over operating temperature range. Refer to the AC ’97 specifications (Revision 2.3, Release 1.0) for further information. The

specification can be downloaded from http://developer.intel.com/ial.scalableplatforms/audio.

RESET

BIT_CLK

Figure 2. Cold Reset Timing (CODEC is Supplying the BIT_CLK Signal)

Table 14.

Symbol

Parameter

Min

Typ

Max

Unit

Recommended During Active (Low) RESET Signal

1.0

µS

RESET Inactive (High) to BIT_CLK Active

162.8

400,000

nS

SYNC

BIT_CLK

Figure 3. Warm Reset Timing

Table 15.

Symbol

Parameter

Min

Typ

Max

Unit

Sync Active (High) Pulse Width

1.3

µS

Sync Inactive to BITCLK Startup Delay

162.8

nS

Hi-Z

RESET

SDATA_OUT

SYNC

BIT_CLK, EAPD,

SPDIF_OUT,

SDATA_IN,

DIGITAL I/O

re 4. ATE Test Mode

Table 16.

Symbol

Parameter

Min

Typ

Max

Unit

Figu

Setup to RESET Inactive (SYNC, SDATA_OUT)

15

nS

Rising Edge of RESET to Hi-Z Delay

25

nS