ISPLSI1032-90LGI datasheet(8/16 Pages) LATTICE

Part #	ISPLSI1032-90LGI

Description	In-System Programmable High Density PLD

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Manufacturer	LATTICE [Lattice Semiconductor]

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Specifications ispLSI 1032

8

ispLSI 1032 Timing Model

GLB Reg

Delay

I/O Pin

(Output)

ORP

Delay

Feedback

4 PT Bypass

20 PT

XOR Delays

Control

PTs

GRP

Loading

Delay

Input

Register

Clock

Distribution

I/O Pin

(Input)

Y0

Y1,2,3

D

Q

GRP 4

GLB Reg Bypass

ORP Bypass

DQ

RST

RE

OE

CK

I/O Reg Bypass

I/O Cell

ORP

GLB

GRP

I/O Cell

#21 - 25

#27, 29,

30, 31, 32

#28

#33

#34, 35, 36

#51, 52,

53, 54

#42, 43,

44

#50

#45

#46

Reset

Ded. In

#26

#20

RST

#55

#37

#38, 39,

40, 41

#48, 49

#47

Derivations of

tsu, th and tco from the Product Term Clock1

tsu

= Logic + Reg su - Clock (min)

=

(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min))

=

(#20 + #28 + #35) + (#38) - (#20 + #28 + #44)

5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (2.0 + 2.0 + 3.5)

th

= Clock (max) + Reg h - Logic

=

(tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

=

(#20 + #28 + #44) + (#39) - (#20 + #28 + #35)

4.0 ns = (2.0 + 2.0 + 7.5) + (4.5) - (2.0 + 2.0 + 8.0)

tco

= Clock (max) + Reg co + Output

=

(tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob)

=

(#20 + #28 + #44) + (#40) + (#45 + #47)

19.0 ns = (2.0+ 2.0 +7.5) + (2.0) + (2.5 + 3.0)

Derivations of

tsu, th and tco from the Clock GLB1

tsu

= Logic + Reg su - Clock (min)

=

(tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min))

=

(#20 + #28 + #35) + (#38) - (#50 + #40 + #52)

5.5 ns = (2.0 + 2.0 + 8.0) + (1.0) - (4.5 + 2.0 + 1.0)

th

= Clock (max) + Reg h - Logic

=

(tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor)

=

(#50 + #40 + #52) + (#39) - (#20 + #28 + #35)

4.0 ns = (4.5 + 2.0 + 5.0) + (4.5) - (2.0 + 2.0 + 8.0)

tco

= Clock (max) + Reg co + Output

=

(tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob)

=

(#50 + #40 + #52) + (#40) + (#45 + #47)

19.0 ns = (4.5 + 2.0 + 5.0) + (2.0) + (2.5 + 3.0)

1. Calculations are based upon timing specifications for the ispLSI 1032-80.

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ISPLSI1032-90LGI Datasheet(PDF) 8 Page - Lattice Semiconductor

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