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ISPLSI1032-80LJ Datasheet(PDF) 11 Page - Lattice Semiconductor |
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ISPLSI1032-80LJ Datasheet(HTML) 11 Page - Lattice Semiconductor |
11 / 16 page Specifications ispLSI 1032 11 Pin Description Input —Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK options become active. Input —This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI/IN 0 also is used as one of the two control pins for the isp state machine. Input —This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. Input/Output —This pin performs two functions. It is a dedicated input pin when ispEN is logic high. When ispEN is logic low, it functions as an output pin to read serial shift register data. Input —This pin performs two functions. It is a dedicated input when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. No Connect Description TQFP Pin Numbers Name Input/Output Pins - These are the general purpose I/O pins used by the logic array. I/O 0 - I/O 3 17, 18, 19, 20, I/O 4 - I/O 7 21, 22, 23, 28, I/O 8 - I/O 11 29, 30, 31, 32, I/O 12 - I/O 15 33, 34, 35, 36, I/O 16 - I/O 19 40, 41, 42, 43, I/O 20 - I/O 23 44, 45, 46, 47, I/O 24 - I/O 27 48, 53, 54, 55, I/O 28 - I/O 31 56, 57, 58, 59, I/O 32 - I/O 35 67, 68, 69, 70, I/O 36 - I/O 39 71, 72, 73, 78, I/O 40 - I/O 43 79, 80, 81, 82, I/O 44 - I/O 47 83, 84, 85, 86, I/O 48 - I/O 51 90, 91, 92, 93, I/O 52 - I/O 55 94, 95, 96, 97, I/O 56 - I/O 59 98, 3, 4, 5, I/O 60 - I/O 63 6, 7, 8, 9 IN 4 - IN 7 66, 87, 89, 10 Dedicated input pins to the device. ispEN 14 SDI/IN 01 16 MODE/IN 11 37 SDO/IN 21 39 SCLK/IN 3 1 60 NC2 1, 2, 24, 25, 26, 27, 49, 50, 51, 52, 74, 75 76, 77, 99, 100 Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any GLB and/or any I/O cell on the device. Dedicated Clock input. This clock input is brought into the clock distribution network, and can optionally be routed to any I/O cell on the device. RESET 15 Y0 11 Y1 65 Y2 62 Y3 61 GND 13, 38, 63, 88 VCC 12, 64 Ground (GND) V CC 1. Pins have dual function capability 2. NC pins are not to be connected to any active signals, Vcc or GND. |
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