Philips Semiconductors

Product specification

89C51/89C52/89C54/89C58

80C51 8-bit microcontroller family

4K/8K/16K/32K Flash

1999 Oct 27

9

TIMER 2 OPERATION

Timer 2

Timer 2 is a 16-bit Timer/Counter which can operate as either an

event timer or an event counter, as selected by C/T2* in the special

function register T2CON (see Figure 1). Timer 2 has three operating

modes: Capture, Auto-reload (up or down counting), and Baud Rate

Generator, which are selected by bits in the T2CON as shown in

Table 3.

Capture Mode

In the capture mode there are two options which are selected by bit

EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or

counter (as selected by C/T2* in T2CON) which, upon overflowing

sets bit TF2, the timer 2 overflow bit. This bit can be used to

generate an interrupt (by enabling the Timer 2 interrupt bit in the

IE register). If EXEN2= 1, Timer 2 operates as described above, but

with the added feature that a 1- to -0 transition at external input

T2EX causes the current value in the Timer 2 registers, TL2 and

TH2, to be captured into registers RCAP2L and RCAP2H,

respectively. In addition, the transition at T2EX causes bit EXF2 in

T2CON to be set, and EXF2 like TF2 can generate an interrupt

(which vectors to the same location as Timer 2 overflow interrupt.

The Timer 2 interrupt service routine can interrogate TF2 and EXF2

to determine which event caused the interrupt). The capture mode is

illustrated in Figure 2 (There is no reload value for TL2 and TH2 in

this mode. Even when a capture event occurs from T2EX, the

counter keeps on counting T2EX pin transitions or osc/12 pulses.).

Auto-Reload Mode (Up or Down Counter)

In the 16-bit auto-reload mode, Timer 2 can be configured (as either

a timer or counter [C/T2* in T2CON]) then programmed to count up

or down. The counting direction is determined by bit DCEN (Down

Counter Enable) which is located in the T2MOD register (see

Figure 3). When reset is applied the DCEN=0 which means Timer 2

will default to counting up. If DCEN bit is set, Timer 2 can count up

or down depending on the value of the T2EX pin.

Figure 4 shows Timer 2 which will count up automatically since

DCEN=0. In this mode there are two options selected by bit EXEN2

in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH

and sets the TF2 (Overflow Flag) bit upon overflow. This causes the

Timer 2 registers to be reloaded with the 16-bit value in RCAP2L

and RCAP2H. The values in RCAP2L and RCAP2H are preset by

software means.

If EXEN2=1, then a 16-bit reload can be triggered either by an

overflow or by a 1-to-0 transition at input T2EX. This transition also

sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be

generated when either TF2 or EXF2 are 1.

In Figure 5 DCEN=1 which enables Timer 2 to count up or down.

This mode allows pin T2EX to control the direction of count. When a

logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will

overflow at 0FFFFH and set the TF2 flag, which can then generate

an interrupt, if the interrupt is enabled. This timer overflow also

causes the 16–bit value in RCAP2L and RCAP2H to be reloaded

into the timer registers TL2 and TH2.

When a logic 0 is applied at pin T2EX this causes Timer 2 to count

down. The timer will underflow when TL2 and TH2 become equal to

the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets

the TF2 flag and causes 0FFFFH to be reloaded into the timer

registers TL2 and TH2.

The external flag EXF2 toggles when Timer 2 underflows or

overflows. This EXF2 bit can be used as a 17th bit of resolution if

needed. The EXF2 flag does not generate an interrupt in this mode

of operation.

(MSB)

(LSB)

Symbol

Position

Name and Significance

TF2

T2CON.7

Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set

when either RCLK or TCLK = 1.

EXF2

T2CON.6

Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and

EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2

interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down

counter mode (DCEN = 1).

RCLK

T2CON.5

Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock

in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

TCLK

T2CON.4

Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock

in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

EXEN2

T2CON.3

Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative

transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to

ignore events at T2EX.

TR2

T2CON.2

Start/stop control for Timer 2. A logic 1 starts the timer.

C/T2

T2CON.1

Timer or counter select. (Timer 2)

0 = Internal timer (OSC/12)

1 = External event counter (falling edge triggered).

CP/RL2

T2CON.0

Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When

cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when

EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload

on Timer 2 overflow.

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2

CP/RL2

SU00728

Figure 1. Timer/Counter 2 (T2CON) Control Register