Philips Semiconductors

Product specification

83C750/87C750

80C51 8-bit microcontroller family

1K/64 OTP/ROM, low pin count

1998 May 01

5

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the

instruction to invoke power-down is the last instruction executed.

Only the contents of the on-chip RAM are preserved. A hardware

reset is the only way to terminate the power-down mode. the control

bits for the reduced power modes are in the special function register

PCON.

Table 1.

External Pin Status During Idle and

Power-Down Modes

MODE

Port 0

Port 1

Port 2

Idle

Data

Data

Data

Power-down

Data

Data

Data

DIFFERENCES BETWEEN THE 8XC750 AND THE

80C51

Program Memory

On the 8XC750, program memory is 1024 bytes long and is not

externally expandable, so the 80C51 instructions MOVX, LJMP, and

LCALL are not implemented. The only fixed locations in program

memory are the addresses at which execution is taken up in

response to reset and interrupts, which are as follows:

Program Memory

Event

Address

Reset

000

External INT0

003

Counter/timer 0

00B

External INT1

013

Counter/Timer Subsystem

Timer/Counter

The 8XC750 has one timers: a 16-bit timer/counter. The 16-bit

timer/counter’s operation is similar to mode 2 operation on the

80C51, but is extended to 16 bits. The timer/counter is clocked by

either 1/12 the oscillator frequency or by transitions on the T0 pin.

The C/T pin in special function register TCON selects between

these two modes. When the TCON TR bit is set, the timer/counter is

enabled. Register pair TH and TL are incremented by the clock

source. When the register pair overflows, the register pair is

reloaded with the values in registers RTH and RTL. The value in the

reload registers is left unchanged. See the 83C750 counter/timer

block diagram in Figure 1. The TF bit in special function register

TCON is set on counter overflow and, if the interrupt is enabled, will

generate an interrupt.

TCON Register

MSB

LSB

GATE

C/T

TF

TR

IE0

IT0

IE1

IT1

GATE

1 – Timer/counter is enabled only when INT0 pin is high,

and TR is 1.

0 – Timer/counter is enabled when TR is 1.

C/T

1 – Counter/timer operation from T0 pin.

0 – Timer operation from internal clock.

TF

1 – Set on overflow of TH.

0 – Cleared when processor vectors to interrupt routine

and by reset.

TR

1 – Timer/counter enabled.

0 – Timer/counter disabled.

IE0

1 – Edge detected in INT0.

IT0

1 – INT0 is edge triggered.

0 – INT0 is level sensitive.

IE1

1 – Edge detected on INT1.

IT1

1 – INT1 is edge triggered.

0 – INT1 is level sensitive.

These flags are functionally identical to the corresponding 80C51

flags, except that there is only one timer on the 83C750 and the

flags are therefore combined into one register.

Note that the positions of the IE0/IT0 and IE1/IT1 bits are

transposed from the positions used in the standard 80C51 TCON

register.

Interrupt Subsystem – Fixed Priority

The IP register and the 2-level interrupt system of the 80C51 are

eliminated. Simultaneous interrupt conditions are resolved by a

single-level, fixed priority as follows:

Highest priority:

Pin INT0

Counter/timer flag 0

Pin INT1

Special Function Register Addresses

Special function registers for the 8XC750 are identical to those of

the 80C51, except for the changes listed below:

80C51 special function registers not present in the 8XC750 are

TMOD (89), P2 (A0) and IP (B8). The 80C51 registers TH1 and TL1

are replaced with the 87C750 registers RTH and RTL respectively

(refer to Table 2).

OSC

÷ 12

TL

TH

TF

RTL

RTH

T0 Pin

TR

Gate

INT0 Pin

Int.

C/T = 0

C/T = 1

Reload

SU00300

Figure 1.

83C751 Counter/Timer Block Diagram