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P80C528FBB Datasheet(PDF) 2 Page - NXP Semiconductors |
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P80C528FBB Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 26 page Philips Semiconductors Product specification 80C528/83C528 CMOS single-chip 8-bit microcontrollers 2 1995 Feb 02 DESCRIPTION The 8XC528 single-chip 8-bit microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 8XC528 has the same instruction set as the 80C51. Three versions of the derivative exist: • 83C528 — 32k bytes mask programmable ROM • 80C528 — ROMless version of the 83C528 • 87C528 — 32k bytes EPROM (described in a separate data sheet) This device provides architectural enhancements that make it applicable in a variety of applications in consumer, telecom and general control systems, especially in those systems which need large ROM and RAM capacity on-chip. The 8XC528 contains a 32k × 8 ROM (83C528), a 512 × 8 RAM, four 8-bit I/O ports, two 16-bit timer/event counters (identical to the timers of the 80C51), a 16-bit timer (identical to the timer 2 of the 80C52), a watchdog timer with a separate oscillator, a multi-source, two-priority-level, nested interrupt structure, two serial interfaces (UART and I2C-bus), and on-chip oscillator and timing circuits. In addition, the 8XC528 has two software selectable modes of power reduction — idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. FEATURES • 80C51 instruction set – 32k × 8 ROM (83C528) – ROMless (80C528) – 512 × 8 RAM – Memory addressing capability 64k ROM and 64k RAM – Three 16-bit counter/timers – On-chip watchdog timer with oscillator – Full duplex UART – I2C serial interface – Four 8-bit I/O ports • Power control modes: – Idle mode – Power-down mode – Warm start from power-down • CMOS and TTL compatible • Extended temperature ranges • ROM code protection • 7-source and 7-vector interrupt structure with 2 priority levels • Up to 3 external interrupt request inputs • Two programmable power reduction modes (Idle and Power-down) • Termination of Idle mode by any interrupt, external or WDT (watchdog) reset • XTAL frequency range: 1.2 MHz to 16 MHz PIN CONFIGURATIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 SDA/P1.7 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD DUAL IN-LINE PACKAGE QUAD FLAT PACK 44 34 1 11 33 23 12 22 LEADED CHIP CARRIER 6 1 40 7 17 39 29 18 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 SCL/P1.6 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 SDA/P1.7 WR/P3.6 RD/P3.7 XTAL2 XTAL1 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VDD SHRINK DUAL IN-LINE PACKAGE 21 22 VSS P2.0/A8 NC* NC* * DO NOT CONNECT |
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