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80C550 Datasheet(PDF) 5 Page - NXP Semiconductors

Part No. 80C550
Description  80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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Philips Semiconductors
Product specification
80C550/83C550/87C550
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, 8 channel 8 bit A/D, watchdog timer
1998 May 01
5
PIN DESCRIPTION
PIN NO.
MNEMONIC
DIP
LCC
TYPE
NAME AND FUNCTION
VSS
20
24
I
Ground: 0V reference.
VCC
40
44
I
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
AVCC
1
1
I
Analog Power Supply: Analog supply voltage.
AVSS
2
4
I
Analog Ground: Analog 0V reference.
Vref+
Vref–
2
3
I
I
Vref: A/D converter reference level inputs. Note that these references are combined with AVCC and
AVSS in the 40-pin DIP package.
P0.0–0.7
39–32
43–36
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float
and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and
data bus during accesses to external program and data memory. In this application, it uses strong
internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in
the S87C550. External pull-ups are required during program verification.
P1.0–P1.7
3–8
5–12
I
Port 1: Port 1 is an 8-bit input only port (6-bit in the DIP package; bits P1.6 and P1.7 are not
implemented). Port 1 digital input can be read out any time.
ADC0–ADC7
3–8
5–12
ADCx: Inputs to the analog multiplexer input of the 8-bit A/D. There are only six A/D inputs in the
DIP package.
P2.0–P2.7
21–28
25–32
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that
are externally being pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to
external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2
special function register.
P3.0–P3.7
10–17
14–21
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that
are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also serves the special features of the SC80C51 family, as listed below:
10
14
I
RxD (P3.0): Serial input port
11
15
O
TxD (P3.1): Serial output port
12
16
I
INT0 (P3.2): External interrupt
13
17
I
INT1 (P3.3): External interrupt
14
18
I
T0 (P3.4): Timer 0 external input
15
19
I
T1 (P3.5): Timer 1 external input
16
20
O
WR (P3.6): External data memory write strobe
17
21
O
RD (P3.7): External data memory read strobe
RST
9
13
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to
VCC.
ALE/PROG
30
34
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program pulse input
(PROG) during EPROM programming.
PSEN
29
33
O
Program Store Enable: The read strobe to external program memory. When the device is
executing code from the external program memory, PSEN is activated twice each machine cycle,
except that two PSEN activations are skipped during each access to external data memory. PSEN
is not activated during fetches from internal program memory.
EA/VPP
31
35
I
External Access Enable/Programming Supply Voltage: EA must be externally held low to enable
the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held
high, the device executes from internal program memory unless the program counter contains an
address greater than 0FFFH. For the 80C550 ROMless part, EA must be held low for the part to
operate properly. This pin also receives the 12.75V programming supply voltage (VPP) during
EPROM programming.
XTAL1
19
23
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
XTAL2
18
22
O
Crystal 2: Output from the inverting oscillator amplifier.




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