 |
 |
|
| MC74F112 |
|
|||||||||||
 MOTOROLA
|
| |||||||||||
|
1 page 
4-45 FAST AND LS TTL DATA DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The MC74F112 contains two independent, high-speed JK flip-flops with Di- rect Set and Clear inputs. Synchronous state changes are initiated by the fal- ling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. SD1 2 1 3 4 6 7 8 GND CP1 J1 K1 Q1 Q1 Q2 5 CP CD CONNECTION DIAGRAM SD J K Q 15 16 14 13 11 10 9 VCC CD1 CD2 CP2 J2 Q2 12 SD2 K2 Q CP SD CD K J Q Q FUNCTION TABLE (Each Half) Inputs Output @ tn @ tn + 1 J K Q L L Qn L H L H L H H H Qn H = HIGH Voltage Level L = LOW Voltage Level tn = Bit time before clock pulse tn + 1 = Bit time after clock pulse J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08 16 1 16 1 16 1 D SUFFIX SOIC CASE 751B-03 5 9 MC74FXXXJ Ceramic MC74FXXXN Plastic MC74FXXXD SOIC MC74F112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP FAST ™ SCHOTTKY TTL ORDERING INFORMATION LOGIC SYMBOL 4 6 1 3 15 10 11 13 7 14 VCC = PIN 16 GND = PIN 8 SD J CP Q Q SD J CP Q Q CD 2 12 K K Asynchronous Inputs: LOW Input to SD sets Q to HIGH level LOW Input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH |
