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SA56606-30 Datasheet(PDF) 7 Page - NXP Semiconductors

Part # SA56606-30
Description  CMOS system reset
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SA56606-30 Datasheet(HTML) 7 Page - NXP Semiconductors

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Product data
SA56606-XX
CMOS system reset
2001 Jun 19
7
TECHNICAL DESCRIPTION
The SA56606-XX is a CMOS device designed to provide power
source monitoring and a system reset function in the event the
supply voltage sags below an acceptable level for the system to
reliably operate. The device is designed to generate a compatible
reset signal for a wide variety of microprocessor and logic systems.
The SA56606 can operate at voltages up to 12 volts. The series
includes several versions providing precision threshold voltage reset
values of 2.0, 2.7, 2.8, 2.9, 3.0, 3.1, 4.2, 4.6 and 4.7 V. The reset
threshold incorporates a typical hysteresis of (VS × 0.05) volts to
prevent erratic resets from being generated.
The output of the SA56606 utilizes a low side open drain topology,
which requires an external pull-up resistor (RPU) to the VDD power
source. Although this may be regarded as a disadvantage, it is an
advantage in many sensitive applications because the open drain
output cannot source reset current to a microprocessor when both
are operated from a common supply. For this reason the SA56606
offers a safe inter-connect to a wide variety of microprocessors.
The SA56606 operates at very low supply currents, typically
0.25
µA, while offering a high precision of threshold detection (±2%).
Figure 12 is a functional block diagram of the SA56606. The internal
reference source voltage (VREF) is typically 0.8 V over the operating
temperature range. The reference voltage is connected to the
non-inverting input of the threshold comparator, while the inverting
input monitors the supply voltage through a resistor divider network
made up of R1, R2, and R3. The output of the threshold comparator
drives the output Open Drain N-Channel FET of the device TR1).
When the supply voltage sags to the threshold detection voltage, the
resistor divider network supplies a voltage to the inverting input of
the threshold comparator, which is less than that of VREF, causing
the output of the comparator to go to a HIGH output state. This
causes the low side N-Channel FET to be active ON, pulling its
drain voltage to a LOW state. The device adheres to a true
input/output logic protocol: the output goes LOW when input is LOW
(below threshold) and output goes HIGH when input is HIGH (above
threshold).
The low side N-Channel FET (TR2) establishes threshold hysteresis
by turning ON whenever the threshold comparator’s output goes to
a HIGH state (when VDD sags to or below the threshold level). TR2’s
turning ON causes additional current to flow through resistors R1 and
R2, causing the inverting input of the threshold comparator to be
pulled even lower. For the comparator to reverse its output polarity
and turn OFF TR2, the VDD source voltage must overcome this
additional pull-down voltage present on the comparator’s inverting
input. The differential voltage required to do this establishes the
hysteresis voltage of the sensed threshold voltage. Typically it is
(VS × 0.05) volts.
When the VDD voltage sags, and is at or below the Detection
Threshold (VSL), the device will assert a Reset LOW output at or
very near ground potential. As the VDD voltage rises from
(VDD < VSL) to VSH or higher, the Reset is released and the output
follows VDD. Conversely, decreases in VDD from (VDD > VSL) to VSL
or lower cause the output to be pulled to ground.
Hysteresis Voltage = Release Voltage – Detection Threshold Voltage
VHYS = VSH – VSL
where:
VSH = VSL + VHYS VREF(R1 + R2) / R2
VSL = VREF(R1 + R2 + R3) / (R2 + R3)
When VDD drops to levels below the minimum operating voltage,
typically less than 0.95 volts, the output is undefined and output
reset LOW assertion is not guaranteed. At this level of VDD the
output will try to rise to VDD.
The VREF voltage is typically 0.8 V. The devices are fabricated using
a high resistance CMOS process and utilize high resistance R1, R2,
and R3 values requiring very small amounts of current. This
combination achieves very efficient low power performance over the
full operating temperature.
SL01323
VDD
VSS
VREF
SA56606-XX
VOUT
1
R2
R1
R
R3
TR1
TR2
3
2
Figure 12. Functional diagram.


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