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TSB41AB2 Datasheet(PDF) 47 Page - Texas Instruments |
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TSB41AB2 Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 50 page  TSB41AB2, TSB41AB2I IEEE 1394a2000 TWOPORT CABLE TRANSCEIVER/ARBITER SLLS424G − JUNE 2000 − REVISED DECEMBER 2004 47 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION LPS CTL0 LREQ SYSCLK D0−D7 CTL1 (1) (2) (3) (4) (high) TCLK_ACTIVE 7 Cycles ISO Figure 27. Interface Initialization, ISO High The sequence of events for initialization of the PHY-LLC interface when the interface is in the nondifferentiated mode of operation (ISO terminal is high) is as follows: 1. LPS reasserted. After the interface has been in the reset or disabled state for at least the minimum TRESTORE time, the LLC causes the interface to be initialized and restored to normal operation by reasserting the LPS signal. In Figure 27, the interface is shown in the disabled state with SYSCLK low inactive. However, the interface initialization sequence described here is also executed if the interface is merely reset but not yet disabled. 2. SYSCLK activated. If the interface is disabled, the PHY reactivates its SYSCLK output when it detects that LPS has been reasserted. If the PHY has entered a low-power state, it takes between 5.3 ms to 7.3 ms for SYSCLK to be restored; if the PHY is not in a low-power state, SYSCLK is restored within 60 ns. The SYSCLK output is a 50% duty cycle square wave with a frequency of 49.152 MHz ±100 ppm (period of 20.345 ns). During the first seven cycles of SYSCLK, the PHY continues to drive the CTL and D terminals low. The LLC is also required to drive its CTL and D outputs low for one of the first six cycles of SYSCLK but to otherwise place its CTL and D outputs in a high-impedance state. The LLC continues to drive its LREQ output low during this time. 3. Receive indicated. Upon the eighth SYSCLK cycle following reassertion of LPS, the PHY asserts the Receive state on the CTL lines and the data-on indication (all ones) on the D lines for one or more cycles. 4. Initialization complete. The PHY asserts the idle state on the CTL lines and logic 0 on the D lines. This indicates that the PHY-LLC interface initialization is complete and normal operation may commence. The PHY now accepts requests from the LLC via the LREQ line. |
Similar Part No. - TSB41AB2 |
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Similar Description - TSB41AB2 |
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