MC74LVX259DR2 datasheet(6/11 Pages) ONSEMI

Part #	MC74LVX259DR2

Description	8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter

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MC74LVX259

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TIMING REQUIREMENTS Input tr = tf = 3.0 ns

TA = 25°C

TA = ≤ 85°C

Symbol

Parameter

Test Conditions

Min

Typ

Max

Min

Max

Unit

tw

Minimum Pulse Width,

Reset or Enable

VCC = 2.7 V

4.5

5.0

ns

Reset or Enable

(Figure 8)

VCC = 3.3 V ± 0.3 V

4.5

5.0

tsu

Minimum Setup Time,

Address or Data to Enable

VCC = 2.7 V

4.0

ns

Address or Data to Enable

(Figure 8)

VCC = 3.3 V ± 0.3 V

3.0

th

Minimum Hold Time,

Enable to Address or Data

VCC = 2.7 V

2.0

ns

Enable to Address or Data

(Figure 7 or 8)

VCC = 3.3 V ± 0.3 V

2.0

tr, tf

Maximum Input,

Rise and Fall Times

VCC = 2.7 V

400

300

ns

Rise and Fall Times

(Figure 5)

VCC = 3.3 V ± 0.3 V

300

*Includes all probe and jig capacitance

Figure 5. Switching Waveform

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Q

DATA

IN

50%

tPLH

tPHL

tf

GND

VCC

50%

Figure 6. Switching Waveform

tr

50%

tPHL

50%

tPHL

DATA

IN

ADDRESS

SELECT

OUTPUT

Q

VCC

GND

VCC

GND

VCC

GND

Figure 7. Switching Waveform

Figure 8. Switching Waveform

Figure 9. Switching Waveform

50%

tw

50%

tPHL

DATA IN

OUTPUT Q

RESET

VCC

GND

VCC

GND

VCC

GND

VCC

GN

D

DATA IN

OUTPUT Q

ENABLE

DATA IN OR

ADDRESS

SELECT

ENABLE

VCC

GND

VCC

GND

tw

50%

tPHL

50%

tsu

th(H)

tsu

Figure 10. Test Circuit

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